PTAB

IPR2016-01622

Kingston Technology Co Inc v. Polaris Innovations Ltd

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Electronic Printed Circuit Board Having a Plurality of Identically Designed, Housing-Encapsulated Semiconductor Memories
  • Brief Description: The ’414 patent describes a printed circuit board (PCB) for a memory module, such as a DIMM, designed to reduce the overall height of the board. The purported invention arranges at least nine identically designed semiconductor memories such that one designated as an error correction chip is oriented vertically (longer dimension perpendicular to the contact strip), while the other memory chips are oriented horizontally (longer dimension parallel to the contact strip).

3. Grounds for Unpatentability

Ground 1: Claims 1-8 are obvious over Simpson

  • Prior Art Relied Upon: Simpson (UK Patent Application GB 2 289 573 A).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Simpson, a 1995 publication describing a customizable memory module, teaches every element of the challenged claims. Simpson discloses a PCB with nine identical memory devices on one face: eight standard memory chips and one "parity memory device" (16a) for error checking. Crucially, Simpson’s figures show the parity memory device oriented with its longer dimension perpendicular to the contact strip, while the sockets for the other eight memory devices are oriented with their longer dimensions parallel to the contact strip. This directly maps to the core arrangement claimed in the ’414 patent.
    • Motivation to Combine (for §103 grounds): As a single-reference ground, the argument was that any minor differences between Simpson and the claims would have been obvious modifications. For example, Petitioner contended that a person of ordinary skill in the art (POSITA) would recognize a parity memory device as a type of error correction chip. For dependent claims, such as claim 2 (requiring the error chip to extend further from the contact strip), Petitioner argued this is an obvious design choice achievable in Simpson by simply omitting certain optional memory chips, as Simpson itself suggests.
    • Expectation of Success (for §103 grounds): A POSITA would have had a high expectation of success in implementing the claimed configuration, as Simpson already depicted the fundamental layout and described the components as standard and interchangeable.

Ground 2: Claims 1-8 are obvious over Simpson in view of the Intel Specification

  • Prior Art Relied Upon: Simpson (UK Patent Application GB 2 289 573 A) and the Intel Specification (PC SDRAM Unbuffered DIMM Specification, Rev. 1.0, 1998).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground asserted that to the extent Simpson alone does not teach certain dimensional limitations of the dependent claims, the Intel Specification provides the missing details. The Intel Specification was an industry standard defining the precise mechanical and electrical requirements for DIMMs, including specific ranges for module height (1.0 to 1.5 inches) and width (approx. 5.25 inches). These standard dimensions directly teach or suggest the limitations recited in dependent claims 4 and 8. The specification also details safety clearances of less than 2 mm, as recited in dependent claim 3.
    • Motivation to Combine (for §103 grounds): A POSITA would combine Simpson with the Intel Specification to modernize Simpson's older design and ensure its compatibility with contemporary computer systems. Adhering to industry standards like the Intel Specification was a routine and necessary step for designing commercially viable memory modules.
    • Expectation of Success (for §103 grounds): A POSITA would have a reasonable expectation of success because applying standardized dimensions and tolerances from the Intel Specification to the known layout of Simpson would not present any technical difficulties. The Intel Specification provides a clear blueprint for manufacturing a standard DIMM.

Ground 3: Claims 1-8 are obvious over the Intel Specification alone

  • Prior Art Relied Upon: Intel Specification (PC SDRAM Unbuffered DIMM Specification, Rev. 1.0, 1998).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that the Intel Specification, by itself, renders the claims obvious. The specification discloses a standard DIMM layout with nine memory devices, including one designated for an ECC (error correction code) chip. While the Intel Specification depicts all chips in a uniform orientation, Petitioner contended that re-orienting the non-ECC chips horizontally was an obvious design choice to achieve the well-known goal of reducing PCB height. A POSITA would know that rotating components is a simple and predictable way to optimize board space.
    • Motivation to Combine (for §103 grounds): This ground relied on a motivation to modify the Intel Specification's design. The motivation was to solve the known problem of reducing component height on a PCB. Choosing between a finite number of orientations (horizontal vs. vertical) to achieve a predictable result (a shorter board profile) would have been an obvious path for a POSITA to pursue ("obvious to try").
    • Expectation of Success (for §103 grounds): A POSITA would have expected success in modifying the orientation of chips on the Intel-specified board, as it involves simple, well-understood layout principles with predictable outcomes on the final board dimensions.

4. Key Claim Construction Positions

  • "Error Correction Chip": Petitioner proposed that this term should be construed to mean "a chip that is able to perform at least error checking on data stored in other semiconductor memories." This construction was based on the ’414 patent’s specification, which describes the chip’s function as checking data correctness. This broad construction was critical to arguing that Simpson’s "parity memory device," which performs error checking, meets the claim limitation.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-8 of Patent 6,850,414 as unpatentable under 35 U.S.C. §103.