PTAB

IPR2017-00032

Samsung Electronics Co Ltd v. ProMOS Technologies Inc

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1. Case Identification

2. Patent Overview

  • Title: Integrated Circuit Comprising a Nonvolatile Memory Cell
  • Brief Description: The ’897 patent discloses a nonvolatile memory cell, such as an EEPROM, with an improved stacked gate structure. The invention addresses problems caused by corrosive byproducts during the formation of a high-temperature oxide layer by introducing a silicon oxynitride (SiON) buffer layer between the polysilicon floating gate and the subsequent dielectric layers.

3. Grounds for Unpatentability

Ground 1: Anticipation of Claim 1 - Claim 1 is anticipated by Ogata under 35 U.S.C. §102.

  • Prior Art Relied Upon: Ogata (Japanese Patent Publication JPH10-154761).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Ogata, which discloses a fabrication method for a non-volatile EEPROM device, teaches every limitation of claim 1. Specifically, Ogata discloses a polysilicon floating gate, a control gate, and an inter-gate dielectric ONO (oxide-nitride-oxide) film. The key disputed element, a "first buffer layer of SiON" in contact with the floating gate, was allegedly disclosed in Ogata as a "thermally nitrided region." Petitioner contended that a person of ordinary skill in the art (POSA) would have understood that forming this region by thermal nitriding of a polysilicon surface using nitrogen monoxide (NO) gas, as taught by Ogata, would necessarily and inherently produce a silicon oxynitride (SiON) layer.
    • Key Aspects: The core of this argument rested on the inherent result of the process disclosed in Ogata. Petitioner asserted that the process of nitriding polysilicon with NO gas was a well-known method for creating SiON films at the time of the invention.

Ground 2: Obviousness of Claims 2 and 3 - Claims 2 and 3 are obvious over Ogata in view of Dong.

  • Prior Art Relied Upon: Ogata (Japanese Patent Publication JPH10-154761) and Dong (Patent 6,187,633).
  • Core Argument for this Ground:
    • Prior Art Mapping: Claim 2 adds a "second buffer layer" located between the silicon nitride layer and the second high-temperature oxide layer of the ONO stack. While Ogata disclosed the base structure of claim 1, it did not teach this second buffer layer. Dong, however, addressed reliability problems in conventional ONO films by disclosing a novel O/N/SiON/O structure, which explicitly forms a "thin silicon oxynitride layer" on top of the silicon nitride layer to reduce pinholes and structural stress. Petitioner argued that combining Dong’s SiON layer with Ogata’s structure would result in the claimed invention. Claim 3, which specifies the second buffer layer is SiON, was argued to be obvious for the same reasons, as Dong’s layer is explicitly SiON.
    • Motivation to Combine: A POSA would combine Ogata and Dong because both references address the fabrication of non-volatile memory devices with well-known ONO dielectric layers. A POSA seeking to improve the reliability and electrical properties of the ONO film in Ogata’s device would have looked to solutions like Dong. A POSA would be motivated to add Dong’s SiON layer to Ogata’s ONO stack to gain the benefits taught by Dong, namely reducing structural stress and eliminating pinholes.
    • Expectation of Success: A POSA would have had a reasonable expectation of success because adding Dong’s SiON layer was a predictable modification to a standard ONO structure and would provide the known benefit of improved dielectric integrity without altering the fundamental operation of Ogata’s memory cell.

Ground 3: Obviousness of Claims 4 and 7 - Claims 4 and 7 are obvious over Ogata in view of Park and Shappir.

  • Prior Art Relied Upon: Ogata (Japanese Patent Publication JPH10-154761), Park (Patent 6,271,091), and Shappir (Patent 5,258,333).

  • Core Argument for this Ground:

    • Prior Art Mapping: Claim 4 adds a "select gate" adjacent to the floating/control gate stack and a "second buffer layer of SiON" under the select gate. Ogata did not disclose a select gate. Park taught the use of a polysilicon select gate, separated by a dielectric layer, adjacent to the floating gate to control the reading and writing of memory cells. Shappir taught an improved composite dielectric layer, comprising a SiON film topped by a high-temperature oxide (HTO) film, for use as a tunnel oxide to improve electrical characteristics like charge trapping. Petitioner argued for a multi-step modification: first, adding Park’s well-known select gate to Ogata’s memory cell for improved control; second, replacing the conventional tunnel oxide layer under the select gate in the combined Ogata/Park device with Shappir’s superior SiON/HTO composite dielectric to achieve better performance and reliability.
    • Motivation to Combine: A POSA would combine Ogata and Park because Ogata’s device lacked a mechanism for selecting memory cells, a known problem for which Park provided a conventional solution. A POSA would then be motivated to improve the underlying dielectric layer of the combined Ogata/Park device to enhance performance. Shappir provided an improved dielectric specifically designed for non-volatile memories, making it an ideal candidate for this modification. Shappir explicitly touted its composite dielectric as exhibiting "excellent electrical characteristics" and having "great potential for use in non-volatile memories."
    • Expectation of Success: The combination was presented as a predictable assembly of known elements. Adding a select gate was a standard design choice, and substituting one dielectric layer for an improved one was a routine modification for a POSA seeking better device performance.

  • Additional Grounds: Petitioner asserted an additional anticipation challenge against claim 1 based on Fuseno (Japanese Patent Publication JPH10-335500) and an obviousness challenge against claim 6 based on the combination of Ogata and Shappir.

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-4, 6, and 7 of the ’897 patent as unpatentable.