PTAB

IPR2017-00039

Samsung Electronics Co Ltd v. ProMOS Technologies Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Sense Amplifier Clock Driver Circuit for Integrated Circuit Memory
  • Brief Description: The ’302 patent is directed to a memory device with circuitry for controlling sense amplifier driver transistors. The invention purports to provide a stable driving signal with a two-stage, controlled rate of change to reduce power consumption, switching noise, and operational instability in high-density memory devices.

3. Grounds for Unpatentability

Ground 1: Claims 14 and 15 are obvious over Min.

  • Prior Art Relied Upon: Min (UK Patent GB2246005B).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Min, a single reference, discloses every limitation of method claims 14 and 15. Min’s sense amplifier driving circuit (FIG. 9) describes a method for generating a control signal that controls driver transistor Q110. The method involves supplying charge at a first rate via transistor Q112 and, after a delay, supplying additional charge at a second rate via transistor Q115. Petitioner asserted that Min explicitly teaches that the first current (IP1) is designed to be smaller than the second current (IP2), directly mapping to the limitation of dependent claim 15 that the first rate is less than the second rate.
    • Motivation to Combine: Although a single reference, the argument relied on combining two disclosed embodiments within Min. Petitioner contended a person of ordinary skill in the art (POSITA) would combine Min’s improved driving circuit (FIG. 9) with its depiction of a conventional sense amplifier array (FIG. 1B). The motivation was to apply Min’s solution to the precise problems Min identified in conventional circuits, such as the one in FIG. 1B.
    • Expectation of Success: A POSITA would have a high expectation of success because the combination involved replacing a standard circuit block (a driver) with an improved version at a well-defined interface (the latch node LAp) to achieve Min's stated goal of stable and rapid driving.

Ground 2: Claims 1-5 and 10-12 are obvious over Min in view of Seo.

  • Prior Art Relied Upon: Min (UK Patent GB2246005B) and Seo (Patent 5,140,199).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued that Min teaches most limitations of the challenged device and clock driver claims, including a circuit with first and second switches (transistors Q112 and Q115) that drive a clock signal through respective impedances. Min’s timing diagrams show that the signal activating the second switch (φSP2) is a delayed version of the signal activating the first switch (φSP1). However, Min does not explicitly disclose the circuit structure for creating this delay. Petitioner asserted that Seo remedies this deficiency. Seo, which also relates to sense amplifier driver circuitry, discloses using a resistor (R3 in FIG. 5) to explicitly generate a delay between two signals. This resistor constitutes the claimed "delay unit."
    • Motivation to Combine: A POSITA seeking to implement the delay function shown in Min’s timing diagrams would have been motivated to look at other prior art in the same field, such as Seo, for a known, simple method to create that delay. Petitioner argued a POSITA would combine Seo’s simple resistor-based delay circuit with Min’s driver to create the delayed signal needed to operate Min's second switch, as this was a common design technique.
    • Expectation of Success: The combination was presented as a simple and predictable modification. Incorporating a standard delay element from Seo into the Min circuit to implement a function already described by Min would have yielded predictable results and was well within the skill of a POSITA.

  • Additional Grounds: Petitioner asserted further obviousness challenges against claims 6, 16-18. These grounds built upon Min by adding single references for specific features: Schuster (a 1986 IEEE journal article) was added to teach a pass transistor coupling a latch node to a data line (for claims 6 and 18), and Tobita (Patent 4,980,799) was added to teach precharging a latch node to an intermediate voltage (for claims 16-17).

4. Key Claim Construction Positions

  • Petitioner argued that several key terms should be construed as means-plus-function limitations under 35 U.S.C. §112, ¶6, because they are generic, nonce words that fail to recite sufficiently definite structure for performing their claimed functions. This was critical to Petitioner's strategy of mapping transistor-based circuits from the prior art onto the functionally-claimed "units" and "components."
  • "timer unit … generating a control signal" (claim 1): Petitioner asserted this term lacks inherent structure. The proposed corresponding structure from the specification was "at least a pair of transistors and one or more circuit components that delay a signal."
  • "first component" and "second component" (claim 1): Petitioner contended these terms are purely functional. The corresponding structures identified in the specification were a "first transistor" and a "second transistor," respectively, which create the two-stage change in the control signal.
  • "delay unit" (claim 10): Petitioner argued this term is functional, with the corresponding structure being "one or more circuit components that delay a signal." This construction allowed Petitioner to map Seo’s resistor R3 to this limitation.

5. Relief Requested

  • Petitioner requested the institution of an inter partes review and the cancellation of claims 1-6, 10-12, and 14-18 of Patent 6,195,302 as unpatentable.