PTAB

IPR2017-00170

Broadcom Corp v. Tessera Advanced Technologies Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Level Shift Circuit
  • Brief Description: The ’699 patent discloses a level shift circuit designed to function as an interface between integrated circuits that operate using different power source voltages. The invention converts a signal from an input-side voltage level to a different, typically higher, output-side voltage level.

3. Grounds for Unpatentability

Ground 1: Anticipation by Kajimoto - Claims 1-2 and 4-9 are anticipated by Kajimoto under 35 U.S.C. § 102.

  • Prior Art Relied Upon: Kajimoto (Japanese Patent Application No. H06-243680).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Kajimoto, which discloses a "signal-level conversion circuit," is structurally identical to the circuit of the ’699 patent. Petitioner presented an element-by-element mapping of Kajimoto's figures to every limitation of independent claims 1 and 8. This mapping identified the input and output side circuits, the corresponding first, second, third, and fourth power sources, and the specific arrangement of the six core transistors (e.g., first and fourth transistors connected between a first power source and a node, etc.). Petitioner asserted that dependent claims were also anticipated, as Kajimoto explicitly discloses using both n-channel and p-channel transistors and describes embodiments where the third power source voltage (Vpp) is higher than the first (Vcc), meeting the limitations of claims 4-7.

Ground 2: Obviousness over Kajimoto and Hashimoto - Claims 3 and 8-12 are obvious over Kajimoto in view of Hashimoto.

  • Prior Art Relied Upon: Kajimoto (Japanese Application No. H06-243680) and Hashimoto (Japanese Application No. S59-216327).
  • Core Argument for this Ground: This ground addressed claims requiring an "inverted" circuit configuration (e.g., swapping p-channel and n-channel transistors) relative to the primary embodiment disclosed in both the ’699 patent and Kajimoto.
    • Prior Art Mapping: Petitioner argued that while Kajimoto taught the fundamental circuit topology, Hashimoto explicitly taught the principle of inverting a level shift circuit. Hashimoto discloses two embodiments: one for shifting a signal to a higher potential and an inverted version for shifting to a lower (negative) potential by swapping NMOS and PMOS transistors and flipping the polarity of the supply voltages. The combination of Kajimoto's circuit and Hashimoto's inversion teaching allegedly rendered the inverted circuit claims obvious.
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine these references as both address level shift circuit design. A POSITA seeking to design a circuit that shifts a signal to a lower or negative voltage (a function described in the ’699 patent's "Third Embodiment") would be motivated to apply Hashimoto's well-known and explicitly taught inversion technique to the base circuit of Kajimoto.
    • Expectation of Success: A POSITA would have a high expectation of success because inverting a complementary MOS (CMOS) circuit was a standard, predictable design practice for achieving a complementary function, as demonstrated by Hashimoto.

Ground 3: Obviousness over Kajimoto and Suma - Claims 13-16 are obvious over Kajimoto in view of Suma.

  • Prior Art Relied Upon: Kajimoto (Japanese Application No. H06-243680) and Suma (Patent 5,770,964).

  • Core Argument for this Ground: This ground addressed claims requiring a plurality of level shift stages connected in series, a configuration described in the ’699 patent as its "Fourth Embodiment."

    • Prior Art Mapping: Petitioner asserted that Kajimoto provided the individual level shift circuit stage. Suma, in its "Tenth Embodiment," was argued to explicitly teach connecting two level shift circuits in series to perform a two-stage voltage conversion. Suma explained that this series configuration enables more reliable and stable operation compared to a single-stage conversion.
    • Motivation to Combine: A POSITA would combine these references to improve the performance and stability of the Kajimoto circuit. It was well-known that making large voltage adjustments in a single step could cause unreliable results. Suma taught using a series connection to stage the voltage shift, a technique a POSITA would readily apply to the Kajimoto circuit to create a more robust design, particularly for applications requiring significant voltage shifts.
    • Expectation of Success: The outcome of connecting Kajimoto circuits in series was entirely predictable, as connecting circuit blocks in series was a fundamental design technique with well-understood results for improving signal integrity and stability.

  • Additional Grounds: Petitioner asserted a final obviousness challenge (Ground 4) for claims 17-19 over Kajimoto in view of both Hashimoto and Suma. This ground argued it would have been obvious to create a series of inverted level shift stages by combining the teachings of all three references.

4. Key Claim Construction Positions

  • Term: "operating by a third power source voltage and a fourth power source voltage which are different from the voltage of the input side circuit."
  • Proposed Construction: Petitioner argued this term should be construed to mean that the third and fourth power source voltages are each different from at least one of the two voltages of the input side circuit.
  • Rationale: This construction was asserted to be necessary because the input circuit operates between two voltages (e.g., Vcc and ground), making the phrase "the voltage" ambiguous. A construction requiring the output voltages to be different from both input voltages would improperly exclude the patent's own preferred embodiments, where the input and output circuits share a common ground voltage.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-19 of Patent 6,043,699 as unpatentable.