Broadcom Ltd v. Invensas Corp

1. Case Identification

• Case #: IPR2017-00171
• Patent #: 6,278,653
• Filed: October 31, 2016
• Petitioner(s): Broadcom Limited
• Patent Owner(s): Invensas Corporation
• Challenged Claims: 1-20

2. Patent Overview

• Title: Reduced Skew Write Timing Scheme for Memory Circuits
• Brief Description: The ’653 patent relates to a write timing scheme for memory circuits designed to reduce signal skew. The invention achieves this by clocking signals on the write data lines and write column select lines using opposite edges of a single clock signal.

3. Grounds for Unpatentability

Ground 1: Claims 1-20 are anticipated by Suzuki under 35 U.S.C. § 102(b).

• Prior Art Relied Upon: Suzuki (Patent 4,916,670).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Suzuki, which discloses a self-timed random access memory (STRAM) device, taught every limitation of the challenged claims. The petition asserted that Suzuki's use of an external clock signal (CLK) and a corresponding inverted clock signal (CLK-bar) to latch different signals at different times directly reads on the ’653 patent’s core method. Specifically, Suzuki's circuit conditions a data signal to become active upon a first transition of the clock (e.g., the falling edge of CLK, which is the rising edge of CLK-bar) and conditions a select signal to become active upon the second, opposite transition (e.g., the rising edge of CLK). This mapping was applied to independent claims 1, 9, and 16, with Petitioner arguing that the dependent claims were also disclosed in Suzuki's detailed circuit diagrams and description.

Ground 2: Claims 2-3, 10-11, and 17-18 are obvious over Suzuki in view of Johnson.

• Prior Art Relied Upon: Suzuki (Patent 4,916,670) and Johnson (a 1993 handbook titled High-Speed Digital Design).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that this combination rendered obvious the challenged claims requiring a specific clock duty cycle. While Suzuki taught using an inverted clock to achieve latching on opposite clock edges for high-speed operation, it did not specify the clock's duty cycle. The challenged dependent claims require a fifty percent duty cycle (or a range of 45-55%). Johnson, a standard reference on high-speed circuit design, was cited for its explicit teaching that "the ideal duty cycle for a clock signal is 50%" and that this feature "permits use of the inverted clock."
  • Motivation to Combine: A POSITA seeking to implement Suzuki’s high-speed memory design would be motivated to optimize its timing margins and reliability. To best utilize the inverted clock taught by Suzuki, the POSITA would naturally consult a foundational design text like Johnson. Applying Johnson’s teaching of an ideal 50% duty cycle to Suzuki’s circuit was presented as a predictable and logical design choice to ensure proper timing and prevent errors.
  • Expectation of Success: Petitioner asserted a high expectation of success, as combining a well-known, ideal clock characteristic with a circuit designed to leverage it would have been a routine optimization for a skilled engineer.

Ground 3: Claims 12 and 16 are obvious over Suzuki in view of Prince.

• Prior Art Relied Upon: Suzuki (Patent 4,916,670) and Prince (a 1997 handbook titled Semiconductor Memories).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground addressed specific structural and method limitations not explicitly detailed in Suzuki. Claim 12 adds a "plurality of additional memory cells all sharing a common column address," and claim 16 recites generating a write data signal and a write column select signal in separate "first" and "second" areas of the circuit. Petitioner argued that Prince taught the fundamental, conventional architecture of SRAMs, which inherently includes arrays with multiple memory cells per column and a physical layout where data path circuitry is distinct from column decoding and selection circuitry.
  • Motivation to Combine: A POSITA would be motivated to implement Suzuki’s novel timing scheme within the standard, well-established SRAM architecture described in Prince. Prince provided the basic structural framework for any SRAM, and it would have been a logical and necessary step to build Suzuki's timing control into this conventional memory array structure to create a functional device.
  • Expectation of Success: Petitioner argued that integrating a specific timing mechanism into a standard memory cell array architecture was a common design task for a memory circuit designer, leading to a high expectation of success.

4. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-20 of Patent 6,278,653 as unpatentable.