PTAB

IPR2017-00297

Apple Inc. v. California Institute of Technology

Title: Serial Concatenation of Interleaved Convolutional Codes Forming Turbo-Like Codes
Brief Description: The ’781 patent discloses methods and systems for error-correcting codes, specifically for what it terms Irregular Repeat-Accumulate (IRA) codes. The technology involves a two-stage encoder where an outer coder irregularly repeats information bits, which are then passed through an interleaver to an inner coder that accumulates them to generate parity bits for error correction in data transmission.

Prior Art Relied Upon: Ping (a 1999 journal article on low-density parity check codes) and Divsalar (a 1998 conference paper on "turbo-like" codes).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Ping teaches a two-step encoding process that meets the core limitations of independent claim 1: a first linear transform operation (a mod-2 summation of information bits) that generates transformed bits, followed by a second accumulation operation that uses those transformed bits as input. The resulting code taught by Ping is a regular code, where each information bit contributes to the same number of parity bits.
- Motivation to Combine: Petitioner asserted a POSITA would combine the teachings of Ping and Divsalar. Divsalar explicitly teaches a well-defined two-step "repeat-and-accumulate" (RA) encoder architecture. This would motivate a POSITA to implement Ping's encoding method using two distinct hardware or software steps, as it simplifies the encoder design and reduces memory requirements. Both references are in the same technical field and share the goal of reducing encoding complexity.
- Expectation of Success: A POSITA would have a high expectation of success because both references operate on the same fundamental principles of error-correcting codes, use similar mathematical operations like mod-2 summation and accumulation, and are directed to improving code performance.

Prior Art Relied Upon: Ping (a 1999 journal article).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner asserted that Ping, by itself, discloses every element of independent claims 19, 20, and 21. The argument centered on mapping Ping's Equation (4), which describes a two-step summation and recursive accumulation process, directly to the claim language. Petitioner contended this equation inherently teaches performing an encoding operation that includes an accumulation of mod-2 sums of bits from subsets of the information bits to generate a codeword, as required by the claims.

Prior Art Relied Upon: Ping (a 1999 journal article), Divsalar (a 1998 conference paper), and MacKay (a 1999 journal article on irregular Gallager codes).
Core Argument for this Ground:
- Prior Art Mapping: This ground specifically targeted claim 9, which adds the limitation of irregularity (i.e., information bits appearing in a "variable number of subsets"). Petitioner established that the base combination of Ping and Divsalar teaches a regular code. MacKay was introduced because it explicitly teaches that irregular codes outperform regular codes and describes how to construct them by designing generator or parity-check matrices with non-uniform column weights.
- Motivation to Combine: A POSITA, starting with the regular code taught by the combination of Ping and Divsalar, would be motivated by MacKay to make the code irregular to achieve superior performance. Petitioner argued this would be a straightforward modification, as it would simply involve changing the generator matrix in Ping to have variable column weights as taught by MacKay, an obvious path to an improved, state-of-the-art code.

Prior Art Relied Upon: Ping (a 1999 journal article), Divsalar (a 1998 conference paper), and Coombes (Patent 4,271,520).
Core Argument for this Ground:
- Prior Art Mapping: This ground addressed limitations in dependent claims 4 and 11 requiring a specific output order for the codeword bits. Claim 4 requires outputting parity bits following the information bits, and claim 11 requires a sequential output of parity bits. Petitioner argued that Coombes explicitly teaches a systematic encoder that outputs a codeword comprised of the original data bits followed by the generated parity bits.
- Motivation to Combine: Petitioner contended that selecting the output order of bits from an encoder is a simple and obvious design choice. A POSITA implementing the encoder of Ping/Divsalar would find it obvious to use the systematic bit order taught by Coombes, as all three references are in the field of error-correcting codes and Coombes provides an explicit, well-known solution for bit ordering.

"codeword" (all claims): Petitioner proposed this term be construed to mean "a discrete encoded sequence of data elements." This was argued to be the plain meaning to a POSITA and consistent with a construction adopted by the district court in related litigation.
"linear transformation" (claim 1): Petitioner proposed this term should be construed as "one that obeys the laws of linear algebra including distributive and associative properties." This construction was asserted to be consistent with the technical definition and a construction previously adopted by the PTAB in a prior IPR involving the ’781 patent.

Petitioner requested institution of an inter partes review and cancellation of claims 3-12 and 19-21 of Patent 7,916,781 as unpatentable.