PTAB

IPR2017-00700

Apple Inc v. California Institute Of Technology

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Serial Concatenation of Interleaved Convolutional Codes Forming Turbo-Like Codes
  • Brief Description: The ’032 patent discloses error-correcting codes, specifically irregular repeat-accumulate (IRA) codes. The described encoder uses a serial concatenation of an outer coder that irregularly repeats message bits, an interleaver that scrambles the repeated bits, and an inner coder (an accumulator) that generates parity bits.

3. Grounds for Unpatentability

Ground 1: Claims 11-12 and 14-16 are obvious over Ping in view of MacKay and Divsalar

  • Prior Art Relied Upon: Ping (a Jan. 1999 journal article), MacKay (a Nov. 1999 journal article), and Divsalar (a Sep. 1998 conference paper).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Ping taught a two-stage encoder with an outer low-density parity-check (LDPC) coder and an inner accumulator, which is recursive. However, Ping’s outer coder was regular, meaning each information bit contributes to the same number of parity bits. The combination with MacKay allegedly rendered Ping’s regular code irregular. Petitioner contended that MacKay expressly taught that irregular codes (with non-uniform column weights in their parity-check matrices) outperform regular codes. Applying MacKay’s teaching to Ping’s generator matrix would result in an irregular code where different message bits contribute to different numbers of parity bits. The combination with Divsalar allegedly supplied the “repeat” function. Petitioner asserted that a POSITA would have found it obvious to implement Ping’s outer coder using Divsalar’s explicit teaching of a repeater, a common and cost-effective component for this purpose. The combination of these references, Petitioner argued, taught all elements of independent claim 11, including its "Tanner graph" limitation, and the dependent claims.
    • Motivation to Combine: A POSITA would combine Ping and MacKay because both references were in the same field of improving LDPC codes, and Ping itself cited the work of MacKay as reviving interest in the field. MacKay’s clear teaching that irregularity improved performance provided a strong motivation to modify Ping’s regular code. A POSITA would incorporate Divsalar’s repeater into the modified Ping design because it provided a known, simple, and efficient method for implementing the repeating/summing function of Ping’s outer coder. The structural similarities between the recursive accumulator codes in Ping and Divsalar further supported their combination.
    • Expectation of Success: A POSITA would have a reasonable expectation of success because MacKay provided experimental results demonstrating the superior performance of irregular codes over regular ones. The combination was presented as the application of a known improvement (irregularity) and a standard implementation technique (repetition) to a known code structure (LDPC-accumulate).

Ground 2: Claim 13 is obvious over Ping in view of MacKay, Divsalar, and Luby97

  • Prior Art Relied Upon: Ping, MacKay, Divsalar, and Luby97 (a 1997 conference paper).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon the combination in Ground 1 to address the additional limitations of claim 13, which required the encoder to receive a "source data stream." Petitioner argued that while Ping taught block-based coding, Luby97 explicitly taught receiving data as a "stream of data symbols" which is then "partitioned... in logical units of blocks."
    • Motivation to Combine: A POSITA would combine Luby97 with the primary combination because, in practice, information bits are often received in a real-time stream. An encoder naturally waits to collect a block of bits from a stream before encoding. Petitioner argued it would have been obvious to adapt the block-based encoder of Ping (as modified by MacKay and Divsalar) to operate on data arriving in a stream, as taught by Luby97, to create a more practical system.
    • Expectation of Success: The modification was a routine design choice to adapt a known coding algorithm for use with a common data input format (a stream), carrying a high expectation of success.

Ground 3: Claim 17 is obvious over Ping in view of MacKay, Divsalar, and Pfister

  • Prior Art Relied Upon: Ping, MacKay, Divsalar, and Pfister (a Sep. 1999 conference paper).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon the combination in Ground 1 to address the additional limitation of claim 17, which required a "second accumulator." Petitioner argued that Pfister taught Repeat-Accumulate-Accumulate (RAA) codes, which were simply Divsalar’s Repeat-Accumulate (RA) codes with an extra accumulator added in series.
    • Motivation to Combine: Pfister explicitly built upon Divsalar and compared the performance of RA codes to its proposed RAA codes. Pfister concluded that adding a second accumulator improved performance. Petitioner contended this provided an explicit suggestion to a POSITA to modify the single-accumulator codes of Divsalar or Ping by adding a second accumulator to gain the performance benefits demonstrated in Pfister.
    • Expectation of Success: Because Pfister provided a direct comparison showing improved performance from adding a second accumulator to a highly similar code structure, a POSITA would have a strong expectation of success.

4. Key Claim Construction Positions

  • "irregular": Petitioner agreed with the Board’s construction from a prior IPR (IPR2015-00060), where the term was construed to mean that "different message bits or groups of message bits contribute to different numbers of parity bits." This construction was central to the argument for combining Ping (regular) with MacKay (teaching irregularity).
  • "Tanner graph": Petitioner asserted that the Board’s prior construction from IPR2015-00060 was the broadest reasonable construction. This construction required, in part, that "a parity bit is determined as a function of both information bits and other parity bits." Petitioner argued this "added constraint" was critical and supported by the ’032 patent’s specification, where each parity bit (after the first) is calculated using the preceding parity bit, which is the definition of an accumulator.

5. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 11-17 of the ’032 patent as unpatentable.