IPR2017-00705
Intel Corp v. R2 Semiconductor Inc
1. Case Identification
- Case #: IPR2017-00705
- Patent #: 8,233,250
- Filed: January 20, 2017
- Petitioner(s): Intel Corporation
- Patent Owner(s): R2 Semiconductor, Inc.
- Challenged Claims: 1-4, 7-9, 13-17, 20-22, and 29
2. Patent Overview
- Title: Voltage Spike Protection Circuitry
- Brief Description: The ’250 patent discloses a voltage regulator with integrated voltage spike protection circuitry, commonly known as a snubber circuit. The invention’s asserted novelty resides in a specific method for selecting the resistance value of a “dissipative element” (resistor) within the snubber circuit, where the value is based on a lumped-element approximation of a transmission line’s characteristic impedance.
3. Grounds for Unpatentability
Ground 1: Claims 1-4, 7-9, 13-17, 20-22, and 29 are obvious over Hibino in view of McMurray.
- Prior Art Relied Upon: Hibino (International Publication No. WO 2009/113298) and McMurray (“Optimum Snubbers for Power Semiconductors,” a 1972 IEEE article).
- Core Argument for this Ground:
Prior Art Mapping: Petitioner argued that the combination of Hibino and McMurray rendered the challenged claims obvious under 35 U.S.C. §103. Hibino disclosed the foundational circuit—a voltage regulator (which it calls a “power converter”) that incorporates snubber circuits comprising resistors and capacitors to reduce surge voltage. This taught the basic structure of a voltage regulator with spike protection circuitry as required by independent claims 1, 13, and 29. Petitioner contended that the sole feature distinguishing the ’250 patent during prosecution was the specific method of calculating the snubber resistor’s value.
This allegedly novel calculation method, however, was explicitly taught decades earlier by McMurray, a widely-cited “classic” reference on snubber circuit design that was not before the Examiner. McMurray taught that the optimal snubber resistor value (R) should be calculated based on the circuit’s characteristic impedance, which is defined as the square root of the circuit's total inductance divided by its capacitance (√(L/C)). McMurray’s equation,
R = 2ζ√(L/C)
, where ζ is the damping factor, directly teaches basing the resistance on the characteristic impedance, as required by claim 1. McMurray further explained that the inductance (L) and capacitance (C) terms are lumped-element approximations representing all relevant circuit inductances (including parasitic inductances from wiring and packaging) and capacitances. This combination directly taught the core limitations of independent claim 1.Petitioner further mapped the combination to key dependent and independent claims. For claim 29’s limitation that the resistance matches the characteristic impedance, Petitioner argued McMurray taught that an “Underdamped Condition” (ζ < 1) is of “most practical importance.” A POSITA would find it obvious to select a damping factor of 0.5, a common value shown in McMurray, which results in the resistance R matching the characteristic impedance (
R = 2 * (0.5) * √(L/C) = √(L/C)
). For claim 16’s requirement of selecting a value to “critically damp” ringing, McMurray explicitly taught that a “critically damped condition” is achieved by selecting a damping factor of 1, making this an obvious design choice. For claims addressing parasitic inductances (e.g., claim 2), Hibino’s disclosure of on-chip implementations and its discussion of wiring inductances, combined with McMurray’s instruction to account for all “circuit inductance,” taught a POSITA to include inductances from the integrated circuit and its package in the calculation.Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) implementing the snubber circuit in Hibino would be motivated to optimize its design to achieve Hibino’s stated goal of reducing surge voltage and protecting switching devices. McMurray provided the exact, well-known, and time-tested design methodology for selecting the snubber resistor value to limit peak voltage and damp oscillations (ringing). Petitioner argued a POSITA would combine Hibino’s circuit with McMurray’s classic design equations as a matter of routine engineering practice to solve the precise problem Hibino addressed.
Expectation of Success: A POSITA would have had a high expectation of success. The combination involved applying a standard mathematical design formula from McMurray to a conventional snubber circuit topology disclosed in Hibino. The electrical principles were well-understood, and their application was routine and predictable in the art of power electronics.
4. Key Claim Construction Positions
- "dissipative element": Petitioner argued this term was central to the invalidity analysis and must be construed as a "resistor." It proposed two alternative constructions. First, it asserted the term is a means-plus-function limitation under §112(f), where the claimed function is to "dissipate energy" and the only corresponding structure disclosed in the ’250 patent specification is a resistor (consistently depicted with the symbol Rsp). Second, if not treated as a means-plus-function term, Petitioner argued that under the broadest reasonable construction, the term must still be interpreted as a "resistor" because the specification and figures exclusively and consistently refer to and depict the "dissipative element" in this manner. This construction was critical to establish that the resistors disclosed in the snubber circuits of Hibino and McMurray met the claim limitation.
5. Relief Requested
- Petitioner requests the institution of an inter partes review and cancellation of claims 1-4, 7-9, 13-17, 20-22, and 29 of the ’250 patent as unpatentable under §103.