PTAB

IPR2017-00730

SK Hynix Inc v. Netlist Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Memory Module with Distributed Data Buffers and Method of Operation
  • Brief Description: The ’632 patent discloses memory modules that use multiple, distributed data buffers to interface between a memory controller and memory devices. To compensate for signal timing differences arising from the distributed layout, each data buffer is configured to determine a time interval during a memory write operation and then use that interval to time the transmission of read data signals during a read operation.

3. Grounds for Unpatentability

Ground 1: Obviousness over Saito and Swain - Claims 1-5, 12-14, and 19-20 are obvious over Saito in view of Swain.

  • Prior Art Relied Upon: Saito (Application # 2010/0309706) and Swain (Patent 7,808,849).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Saito discloses a memory module architecture that meets nearly all limitations of claim 1. Saito describes a module with a central command/address/control register buffer (the claimed "module control device") that sends signals to multiple memory chips arranged in groups, with each group corresponding to a distributed data register buffer. Saito explicitly recognizes that this distributed layout creates signal timing issues and discloses performing "write leveling" and "read leveling" operations during initialization to determine necessary timing adjustments. However, Petitioner contended that Saito determines the timing adjustment for read operations during its read leveling process, not from its write leveling process as required by the claims.
    • Motivation to Combine: Petitioner asserted a person of ordinary skill in the art (POSITA) would combine Saito with Swain to arrive at the claimed invention. Swain, which addresses the same problem of timing adjustments in memory modules, teaches performing write leveling first and then using the "parameters determined while write leveling" to set the timing delay for read operations. Petitioner argued that because Saito teaches that its data transfer rates are identical for read and write operations, a POSITA would have been motivated to apply Swain's more efficient technique to Saito's system. This would avoid the redundant step of measuring the same timing interval twice (once for writes, once for reads), a clear design optimization.
    • Expectation of Success: A POSITA would have a reasonable expectation of success because combining the teachings was a matter of applying a known, advantageous timing method (Swain) to a compatible system (Saito) to achieve the predictable result of increased efficiency without changing the fundamental operation of Saito's module.

Ground 2: Obviousness over Saito, Swain, and Kim - Claims 3, 13, and 14 are obvious over Saito in view of Swain in further view of Kim.

  • Prior Art Relied Upon: Saito (Application # 2010/0309706), Swain (Patent 7,808,849), and Kim (Patent 6,184,701).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground builds upon the Saito/Swain combination from Ground 1 to address the limitations of claims 3, 13, and 14, which require each buffer circuit to include a "metastability detection circuit" and a "signal adjustment circuit." Petitioner first argued that Saito's own Delay-Locked Loop (DLL) circuits inherently meet these limitations by detecting signal misalignments (metastability) and adjusting internal clocks to correct them (signal adjustment). In the alternative, should Saito's DLLs be deemed insufficient, Petitioner argued that Kim explicitly discloses a "metastability detection/prevention circuit" for this exact purpose. Kim teaches that its circuit can be incorporated into any "main active circuit" in need thereof, including a "data input buffer."
    • Motivation to Combine: Petitioner contended that metastability is a well-known problem in digital circuits that arises when signals are transmitted between different clock domains, such as in Saito's data register buffers. A POSITA would be motivated to avoid the resulting communication failures by incorporating a known solution. Kim provides such a solution and expressly teaches its applicability to data buffers. Therefore, a POSITA would find it obvious to integrate Kim's metastability detection circuit into the data register buffers of the Saito/Swain combination to enhance system reliability.
    • Expectation of Success: There would be a high expectation of success in this combination, as it involves incorporating a known solution (Kim's circuit) to address a well-understood problem (metastability) in a standard component (Saito's data buffers).

4. Key Claim Construction Positions

  • "metastability": Petitioner proposed that this term be construed as the "misalignment of a signal from the relevant clock signal." This construction is central to the argument that Saito's DLL circuits, which are designed to detect and correct signal misalignments relative to a clock signal, meet the "metastability detection" limitation of claims 3 and 13.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-5, 12-14, and 19-20 of the ’632 patent as unpatentable.