PTAB

IPR2017-00865

VALEns Semiconductor v. Vesper Technology Research LLC

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Petition
petition Intelligence

1. Case Identification

2. Patent Overview

  • Title: Data Transfer System and Method for Multi-Level Signal of Matrix Display
  • Brief Description: The ’247 patent discloses a data transfer system for driving a matrix display, such as an LCD. The system uses multi-level signaling to encode digital display data into a signal with multiple voltage levels, which reduces the number of required data lines and lowers the data transfer frequency, thereby mitigating electromagnetic interference (EMI).

3. Grounds for Unpatentability

Ground 1: Claims 1-10 are obvious over Go in view of Beers.

  • Prior Art Relied Upon: Go (Patent 6,320,590) and Beers (Patent 5,913,075).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Go disclosed a complete data transfer system for an LCD that uses multi-level signaling to compress data, thereby reducing the number of wires on a data bus to suppress EMI. Go’s system included a bus compressor (encoder) to generate multi-level signals and a bus decompressor (decoder) to reconstruct the data. However, Petitioner contended that Go’s encoder lacked the explicit clocking functionality of the claimed “multi-level timing controller.” Beers was argued to supply this missing element by teaching a controller for converting digital signals into a clocked multi-level signal for transmission over a bus. The express purpose of Beers’ architecture was to reduce the bus cycle rate (frequency) relative to the processor clock rate, effectively addressing EMI caused by high frequencies.
    • Motivation to Combine: Petitioner asserted that a person of ordinary skill in the art (POSITA) would be motivated to combine the teachings of Go and Beers to create a more effective solution for the known problem of EMI in high-speed data transfer systems. Both references address EMI using multi-level signaling but focus on different aspects: Go reduces the number of transmission lines, while Beers reduces the transfer frequency. A POSITA would combine these complementary approaches by substituting Go’s encoder with the clocked multi-level timing controller of Beers. This combination would predictably yield a system with superior EMI performance by addressing both contributing factors—wire count and frequency.
    • Expectation of Success: The proposed combination was presented as a simple substitution of one known type of encoder for another to combine their respective known benefits, leading to a high expectation of success in achieving a more robust system.

Ground 2: Claims 1-10 are obvious over Kuwata in view of Chen.

  • Prior Art Relied Upon: Kuwata (Patent 5,900,857) and Chen (Patent 6,324,602).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Kuwata disclosed a driver circuit for an LCD that used a memory (VRAM) to store and provide image data to the display drivers. Kuwata explicitly identified problems with this approach, including the high cost of VRAM and significant EMI ("radiation noise") resulting from the required high-speed memory access. Chen was argued to provide a direct solution to these identified problems. Chen taught an advanced input/output (I/O) interface for memory devices that uses multi-level signal conversion (bit compression/decompression) to enable high-speed memory access while simultaneously reducing pin count, operating frequency, power consumption, and EMI.
    • Motivation to Combine: A POSITA, when faced with the cost and EMI problems described in Kuwata, would have been motivated to look for improved memory interface solutions like the one disclosed in Chen. Petitioner argued that a POSITA would replace Kuwata’s expensive and noisy VRAM-based memory system with Chen’s advanced I/O interface. This would be a logical design choice to create a lower-cost driver circuit (as Chen’s interface could be used with cheaper DRAM) that maintains high-speed performance while solving the very power consumption and EMI issues that Kuwata highlighted.
    • Expectation of Success: Petitioner asserted that substituting one memory subsystem for an improved one to gain its known advantages was a well-understood design practice. A POSITA would have a reasonable expectation of success in integrating Chen’s interface into Kuwata’s driver circuit to obtain the predictable benefits of lower cost and reduced EMI.

4. Key Claim Construction Positions

  • "matrix display": Petitioner proposed this term be construed as "a display that comprises a plurality of picture element circuits arranged as a matrix, such as a liquid crystal display (LCD)." This construction was based on the patent’s specification, which uses the terms interchangeably.
  • "multi-level": Petitioner proposed the construction "having three or more meaningful levels," arguing this was consistent with the definition the patent owner relied upon during prosecution to overcome a 35 U.S.C. §112 rejection.
  • "multi-level timing controller": This was the most disputed term. Petitioner proposed the construction "a controller for converting digital data to a clocked multi-level signal for transferring over a bus." The inclusion of "clocked" was argued to be essential, based on the specification's description of operating frequency (e.g., "pixel/clock") and the principle of claim differentiation, as dependent claim 2 separately adds the limitation of a "multi-level encoder."

5. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1-10 of Patent 6,611,247 as unpatentable.