Broadcom Ltd v. Tessera Inc

1. Case Identification

• Case #: IPR2017-00889
• Patent #: 6,847,107
• Filed: February 10, 2017
• Petitioner(s): Broadcom Limited
• Patent Owner(s): Tessera, Inc.
• Challenged Claims: 1-8

2. Patent Overview

• Title: Compliant Semiconductor Package Structure
• Brief Description: The ’107 patent relates to semiconductor chip packaging, specifically a compliant package structure for "flip-chip" bonding. The technology aims to mitigate failures caused by thermal stress on rigid solder bonds by interposing a compliant layer on the chip's surface and using bond ribbons to reroute electrical connections from chip contacts to terminal positions on the compliant layer.

3. Grounds for Unpatentability

Ground 1: Anticipation by Yanagihara - Claims 1, 2, 5, 6, and 8 are anticipated by Yanagihara.

• Prior Art Relied Upon: Yanagihara (Japanese Patent Publication No. JPH05-144823).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Yanagihara, which discloses a method for forming high-density bumps on a "flip chip," teaches every limitation of the challenged claims. Yanagihara describes a microelectronic element (chip) with a central region containing a plurality of contacts (pad portions). A compliant "cushion portion" made of photosensitive polyimide overlies the peripheral region of the chip’s surface. This cushion portion has a bottom surface facing the chip, a top surface facing away, and "gently-sloping" edge surfaces extending between them. Finally, Yanagihara discloses forming a conductive circuit of "bond ribbons" that extend from the contacts, over the sloped edge and top surfaces of the cushion, to connect to conductive terminals.
  • Prior Art Mapping (Dependent Claims): Petitioner asserted Yanagihara also explicitly meets the dependent claims. The microelectronic element is disclosed as a semiconductor "chip" (claim 2). Its contacts ("pad portions") are shown spaced apart in an array configuration (claim 5). The compliant layer material, polyimide, is a known thermosetting polymer (claim 6). The bond ribbons are inherently flexible to conform to the topography of the sloping cushion layer and are described as enabling "elastic deformation" to absorb strains, thus meeting the flexibility requirement (claim 8).

Ground 2: Obviousness over Yanagihara and Harada - Claim 3 is obvious over Yanagihara in view of Harada.

• Prior Art Relied Upon: Yanagihara (Japanese Patent Publication No. JPH05-144823) and Harada (Japanese Patent Publication No. JPS64-1257).
• Core Argument for this Ground:
  • Prior Art Mapping: Claim 3 adds the limitation of a dielectric passivation layer situated between the chip surface and the compliant layer, with apertures aligned with the chip's contacts. Petitioner argued that while Yanagihara provides the base structure of claim 1, Harada supplies the missing element. Harada, which also relates to flip-chip devices, explicitly discloses a "passivation film" on the surface of a semiconductor device, with openings that expose the underlying electrodes (contacts). Harada further teaches forming a compliant polyimide layer directly on top of this passivation film to serve as an "impact buffering function." The combination of Yanagihara's structure with Harada's passivation layer results in the structure claimed in claim 3.
  • Motivation to Combine: Petitioner contended that a person of ordinary skill in the art (POSITA) would have been motivated to combine the references. Both Yanagihara and Harada address the same field (flip-chip technology) and the same problem: forming reliable bump connections while minimizing the risk of cracks and mechanical stress. A POSITA seeking to improve the reliability of the structure in Yanagihara would have looked to contemporaneous solutions like Harada, which taught the known benefit of adding a compliant layer over a passivation layer to protect it from cracking.
  • Expectation of Success: A POSITA would have had a reasonable expectation of success in this combination, as it involved applying a known technique (adding a protective compliant layer over a standard passivation layer) to achieve a predictable result (improved device durability).

Ground 3: Obviousness over Yanagihara and Inoue - Claims 4 and 7 are obvious over Yanagihara in view of Inoue.

• Prior Art Relied Upon: Yanagihara (Japanese Patent Publication No. JPH05-144823) and Inoue (Japanese Patent Publication No. JPH02-272737).
• Core Argument for this Ground:
  • Prior Art Mapping: Claims 4 and 7 add a protective top layer over the bond ribbons: an "encapsulant layer" (claim 4) or a "top dielectric layer" (claim 7) that leaves the conductive terminals accessible. Petitioner asserted that Yanagihara provides the underlying assembly, and Inoue teaches the addition of this protective layer. Inoue discloses a method for forming projecting electrodes on a semiconductor chip that includes a final step of forming an "insulation film" (e.g., polyimide) over the entire surface, including the connection patterns (bond ribbons), and then photoetching it to "expose at least a top portion of the projecting electrode" (the terminals). Petitioner argued this insulation film serves as the claimed encapsulant or dielectric layer, meeting the limitations of both claims 4 and 7.
  • Motivation to Combine: Petitioner argued a POSITA would combine these teachings because both references concern flip-chip technology and the formation of bumps or projecting electrodes. Adding a protective encapsulant layer was a well-known practice in the art, often referred to as "flip chip underfill," to protect circuitry from environmental corrosion and enhance the mechanical performance of solder joints. A POSITA would have been motivated to apply Inoue's well-understood encapsulation technique to Yanagihara's structure to gain these predictable benefits.
  • Expectation of Success: The combination was merely the application of a conventional processing step (encapsulation) to a known semiconductor structure. Therefore, a POSITA would have had a high expectation of success in protecting the bond ribbons without disrupting the assembly's function.

4. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-8 of Patent 6,847,107 as unpatentable.