PTAB

IPR2017-01068

LSI Corp v. Regents Of University Of Minnesota

Log In

1. Case Identification

2. Patent Overview

  • Title: Error Detection and Correction System Utilizing a Reed-Solomon Code
  • Brief Description: The ’601 patent describes a decoder for low-density parity-check (LDPC) codes, which are used for error correction in data transmission and storage systems. The invention focuses on a parallel, iterative decoding architecture where messages are passed between variable nodes and check nodes to correct errors in received data.

3. Grounds for Unpatentability

Ground 1: Obviousness over Gallager and Owsley - Claims 1-3, 5, 8, 9, 12, 13, 16, and 17 are obvious over Gallager in view of Owsley.

  • Prior Art Relied Upon: Gallager (Robert G. Gallager, "Low-Density Parity-Check Codes," 1963 Ph.D. Thesis) and Owsley (Patrick A. Owsley, "Parallel Viterbi algorithm and decoder," NASA Tech Briefs, Apr. 1993).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Gallager, the foundational work on LDPC codes, discloses all fundamental elements of the challenged claims. Gallager teaches a decoder comprising variable nodes and check nodes that iteratively pass messages to correct errors in a received signal. This process includes generating initial messages based on the received signal, updating check node messages based on variable node messages, updating variable node messages based on check node messages, and making a final decision after a set number of iterations or when a valid codeword is found. Petitioner asserted that these teachings satisfy the core limitations of independent claims 1, 8, and 12. Owsley, while directed to Viterbi decoders, discloses a parallel hardware architecture for implementing iterative decoding algorithms to increase processing speed. Petitioner contended that Owsley's disclosure of parallel processing units directly maps to the claimed "plurality of processors" operating in parallel to update messages.
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine Gallager's LDPC decoding algorithm with Owsley's parallel processing architecture to achieve higher data throughput. Petitioner argued that increasing decoding speed was a primary objective in the field of error correction, and implementing known algorithms like Gallager's in parallel hardware, as taught by Owsley, was a well-understood and predictable method to achieve this goal. The parallel architecture in Owsley was presented as being applicable to iterative algorithms generally, not just Viterbi decoders.
    • Expectation of Success: A POSITA would have had a high expectation of success. The combination involved applying a known optimization technique (parallel processing) to a known algorithm (LDPC decoding) to achieve a predictable result (increased speed). The implementation would have been a matter of routine engineering, as parallel architectures for similar iterative decoding processes were well-established.

Ground 2: Obviousness over Gallager, Owsley, and Forney - Claim 4 is obvious over Gallager in view of Owsley and Forney.

  • Prior Art Relied Upon: Gallager (1963 Thesis), Owsley (NASA Tech Briefs, Apr. 1993), and Forney (G. David Forney, Jr., "The Viterbi Algorithm," Proceedings of the IEEE, Mar. 1973).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon Ground 1 to address the additional limitation in dependent claim 4, which requires the decoder to operate on "soft decision" inputs. Soft decisions represent the reliability of each received bit, providing more information than simple binary "hard decisions." Petitioner argued that while Gallager primarily focused on a binary channel (hard decisions), Forney explicitly taught the significant performance benefits of using soft-decision information in the context of the Viterbi algorithm. Forney explained that using the reliability of the received data, rather than just a binary value, leads to a substantial improvement in error correction performance. Petitioner contended that this teaching directly satisfies the "soft decision" limitation of claim 4.
    • Motivation to Combine: A POSITA, having already combined Gallager and Owsley to create a high-speed parallel decoder, would be further motivated to incorporate Forney's teaching on soft decisions to improve the decoder's performance. The goal of any error correction system is to minimize errors, and Forney provided a well-known method for achieving superior performance. Applying this known technique to the Gallager/Owsley decoder was presented as a logical and obvious step to create a more robust and effective system.
    • Expectation of Success: The application of soft-decision decoding to iterative algorithms was a known and established practice in the art by the priority date of the ’601 patent. A POSITA would have reasonably expected that incorporating soft-decision inputs, as taught by Forney, into the parallel LDPC decoder of Gallager and Owsley would successfully and predictably enhance its error-correcting capabilities.

4. Relief Requested

  • Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 1-5, 8, 9, 12, 13, 16, and 17 of Patent 5,859,601 as unpatentable.