PTAB

IPR2017-01069

SanDisk LLC v. Memory Technologies LLC

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1. Case Identification

2. Patent Overview

  • Title: Memory Card with Bus Checking Procedure
  • Brief Description: The ’186 patent relates to a system for determining the usable data bus width between a host device and an electronic memory card. The invention purports to overcome prior art methods by using a bus checking procedure that sends test bit patterns to the memory card, which returns a responsive pattern, allowing the host to determine the bus width without reading a dedicated internal register on the card.

3. Grounds for Unpatentability

Ground 1: Obviousness over Lawrence in view of Ishibashi - Claims 16-19 are obvious over Lawrence in view of Ishibashi.

  • Prior Art Relied Upon: Lawrence (Patent 5,995,424) and Ishibashi (Patent 5,630,106).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Lawrence disclosed an automated, portable memory tester for determining memory module characteristics, including data bus width. Lawrence’s CHECK_WIDTH subroutine involved writing a first bit pattern (e.g., hexadecimal ‘A’ or binary ‘1010...’) and a second, complementary pattern to a memory module, reading the patterns back, and comparing them to identify active data lines. Ishibashi disclosed a dynamic random access memory (DRAM) that included a selectable inverting data path, which could be activated by a MODE1 signal to output the logical complement of stored data. Petitioner contended that the combination of using Lawrence's tester on Ishibashi's memory with the inverting path enabled would meet the limitations of independent claim 16. Specifically, Lawrence’s tester would send a "first bit pattern," and Ishibashi’s memory, operating in its inverting mode, would provide a "second bit pattern" that is the "complementary pattern" of the first. The comparison function of Lawrence's tester would then determine the usable bus width based on this predetermined complementary relationship.
    • Motivation to Combine: A POSITA would combine Lawrence’s generic, automated memory tester with Ishibashi’s memory unit to achieve the well-understood benefits of automated testing, such as improved accuracy, reduced testing time, and lower cost. Lawrence’s explicit objective of verifying that no electrical shorts exist on the memory bus would motivate a POSITA to test both the standard non-inverting path and the special-function inverting path of Ishibashi’s memory to ensure its complete functionality and reliability.
    • Expectation of Success: A POSITA would have had a high expectation of success. The interaction between the tester and the memory-inverting circuit was predictable. Modifying Lawrence’s comparison logic (e.g., from a bit-wise OR to a bit-wise AND) to correctly interpret the inverted response from Ishibashi was argued to be a straightforward application of fundamental binary logic principles.

Ground 2: Anticipation by Ishibashi - Claim 16 is anticipated by Ishibashi.

  • Prior Art Relied Upon: Ishibashi (Patent 5,630,106).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground was presented as an alternative argument, contingent on the Board adopting a broad construction of claim 16 where the preamble and "wherein" clause elements related to the "host electronic module" are considered non-limiting language of purpose. Petitioner asserted that if the claim is interpreted as being directed only to a memory unit per se, then Ishibashi alone anticipated every element. Ishibashi’s DRAM was a memory unit that comprised a "receiving mechanism" (its data inputs and multiplexer) for receiving a bit pattern and a "conversion mechanism" (its inverting circuit 103). This conversion mechanism was responsive to a received pattern and capable of providing a second bit pattern on the data bus that was a complementary pattern of the first, thus meeting all limitations of the memory unit itself.
    • Key Aspects: This argument's viability depended entirely on a claim construction theory that divorces the claimed memory unit from the host module functions described in the preamble and the final "wherein" clause of claim 16.

4. Key Claim Construction Positions

  • "receiving mechanism" / "conversion mechanism": Petitioner argued that these terms in independent claim 16 were means-plus-function limitations under 35 U.S.C. § 112, para. 6, as they are nonce terms that do not connote a sufficiently definite structure. For the purposes of its invalidity arguments, Petitioner proposed that the Board adopt broad constructions:
    • "receiving mechanism" should be construed to include any component of a memory unit that can receive a first bit pattern.
    • "conversion mechanism" should be construed to include any component of a memory unit that can provide a second bit pattern that is at least partly complementary to the first.
  • These proposed constructions were critical to Petitioner's arguments, as they allowed Ishibashi's inverting circuit to be mapped to the "conversion mechanism" limitation.

5. Relief Requested

  • Petitioner requested the institution of an inter partes review and the cancellation of claims 16-19 of Patent 7,275,186 as unpatentable under 35 U.S.C. §§ 102 and 103.