PTAB

IPR2017-01111

Amazon.com Inc v. Broadcom Corp

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1. Case Identification

2. Patent Overview

  • Title: Video Decoding System Supporting Multiple Standards
  • Brief Description: The ’844 patent relates to systems for decoding digital video data that support multiple video standards. The system employs a processor to control the overall decoding process and one or more configurable hardware accelerators to facilitate and perform selected decoding tasks according to a plurality of methods or standards.

3. Grounds for Unpatentability

Ground 1: Anticipation of Claims 1-14 - Claims 1-14 are anticipated under 35 U.S.C. §102 by Fandrianto ’459.

  • Prior Art Relied Upon: Fandrianto ’459 (Patent 5,982,459).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued Fandrianto ’459 discloses every element of the challenged claims. Specifically, it teaches a programmable video codec containing a supervisory RISC processor (220) adapted to control a decoding process, satisfying the "processor" limitation of claim 1. Fandrianto ’459 also discloses multiple hardware accelerators coupled to this processor, including a video processor (280), a Huffman codec (260), and an H.221/BCH decoder (240), each adapted to perform decoding functions on a digital media data stream. Petitioner contended these accelerators are configurable to perform their functions according to a plurality of decoding methods (e.g., MPEG, H.261 standards) by executing different software loaded by the RISC processor or using different look-up tables. Petitioner further mapped specific disclosures to the dependent claims, arguing the video processor (280) performs functions such as inverse quantization (claim 11), pixel filtering (claim 11), and de-blocking (claim 12).

Ground 2: Obviousness of Claims 1-4, 6-11, and 13-14 - Claims 1-4, 6-11, and 13-14 are anticipated under §102 by Fandrianto ’842.

  • Prior Art Relied Upon: Fandrianto ’842 (Patent 6,441,842).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted Fandrianto ’842 discloses a "videocommunication" apparatus that meets all limitations of the challenged claims. The vision processor (100) serves as the processor adapted to control decoding. This processor includes a plurality of hardware accelerators within its constituent Control Section (90), Motion Estimation Section (92), and Discrete Cosine Transform (DCT) Section (94). Components within these sections, such as the RISC-type controller (102), shifters (140, 144), arithmetic logic unit (154), and multiplier-accumulator (148), were identified as accelerators that perform decoding functions. Petitioner argued the system is configurable to perform decoding according to a plurality of methods, as it operates in different "modes" (intraframe and predictive) and can be reconfigured for various industry-recognized communication standards, thereby anticipating the claims.

Ground 3: Obviousness of Claims 11-14 - Claims 11-14 are obvious over Fandrianto ’459 in view of Fandrianto ’842.

  • Prior Art Relied Upon: Fandrianto ’459 (Patent 5,982,459) and Fandrianto ’842 (Patent 6,441,842).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued that to the extent Fandrianto ’459 does not explicitly disclose a "motion compensator" as required by claim 11, Fandrianto ’842 remedies this deficiency. Fandrianto ’842 explicitly discloses a motion compensator (e.g., shifter units 140, 142) as part of its Motion Estimation Section (92) to perform motion compensation on a data stream. All other elements of claims 11-14 were argued to be present in Fandrianto ’459 alone.
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine the references because they address analogous problems in the same field of video decoding for applications like videoconferencing. Fandrianto ’842 teaches that motion estimation and motion compensation are related, interchangeable techniques. A POSITA would therefore be motivated to incorporate the well-known motion compensation technique from Fandrianto ’842 into the decoding system of Fandrianto ’459 to improve decoding performance and address known problems like visual redundancy.
    • Expectation of Success: Integrating a standard video decoding component like a motion compensator into a similar existing system was a predictable design choice. Since both patents describe systems for similar applications and use common decoding principles, a POSITA would have had a reasonable expectation of success in combining their teachings.

  • Additional Grounds: Petitioner asserted an additional obviousness challenge (Ground 4) for claims 5 and 12 based on Fandrianto ’842 in view of Fandrianto ’459, relying on similar motivations to add processor-assist and de-blocking filter functionalities to the Fandrianto ’842 system.

4. Key Claim Construction Positions

  • Petitioner proposed that for the purposes of the inter partes review (IPR), the term “accelerator” as used in claims 1-14 should be construed to mean “a device that speeds up or enhances operation.” This broad construction was central to Petitioner’s arguments, as it allowed various processing units disclosed in the prior art (e.g., video processors, codecs, decoders) to be identified as satisfying the “hardware accelerator” limitation of the claims.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-14 of the ’844 patent as unpatentable.