Intel Corp v. R2 Semiconductor Inc

1. Case Identification

• Case #: IPR2017-01123
• Patent #: 8,233,250
• Filed: March 24, 2017
• Petitioner(s): Intel Corporation
• Patent Owner(s): R2 Semiconductor, Inc.
• Challenged Claims: 5-6, 18-19, 27, and 30

2. Patent Overview

• Title: Voltage Spike Protection Circuitry
• Brief Description: The 8,233,250 patent discloses a voltage regulator that includes voltage spike protection circuitry, commonly known as a "snubber circuit." The alleged novelty resides in a method for selecting the resistance value of a "dissipative element" (resistor) within the circuit based on a lumped-element approximation of a transmission line's characteristic impedance, and in the implementation of the circuitry using metal-oxide-semiconductor (MOS) components.

3. Grounds for Unpatentability

Ground 1: Claims 5-6, 18-19, 27, and 30 are obvious over Hibino in view of McMurray and in further view of Wong.

• Prior Art Relied Upon: Hibino (WO 2009/113298), McMurray ("Optimum Snubbers for Power Semiconductors," a 1972 article), and Wong (Patent 5,485,292).
• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner argued that the prior art combination teaches every limitation of the challenged claims. Hibino disclosed the foundational circuit: a voltage regulator (power converter) with snubber circuitry comprising a resistor ("dissipative element") and a capacitor ("charge-storage circuit") to protect against voltage surges. The key limitation added during prosecution—calculating the resistor's value based on characteristic impedance—was not taught by Hibino but was explicitly taught by McMurray. McMurray, described as a "classic" reference, provided the exact formula for determining an optimal snubber resistance based on the square root of the circuit's total inductance (L) divided by its capacitance (C), which is the definition of characteristic impedance. McMurray further taught using a "lumped element approximation" by modeling the total circuit inductance and capacitance as single L and C values. This combination of Hibino and McMurray was argued to render the independent claims from which the challenged claims depend obvious.

    For the dependent claims requiring MOS implementation, Petitioner asserted that Wong taught the remaining limitations. Wong disclosed fabricating high-voltage capacitors using standard MOS technology, specifically by connecting a plurality of poly-poly MOS capacitors in series. This structure divides the total voltage across the series, ensuring the voltage across any single capacitor remains below its breakdown threshold, directly teaching the limitations of claims 6, 19, 27, and 30. Wong's MOS capacitor and the obvious implementation of Hibino’s resistor as a MOS polysilicon resistor together form the "MOS structure" required by claims 5 and 18.

  • Motivation to Combine: Petitioner contended that a person of ordinary skill in the art (POSITA) would have been motivated to combine the references. A POSITA seeking to implement Hibino's snubber circuit would have naturally turned to well-known, foundational design principles, such as those in McMurray, to optimize the resistor value for effective voltage spike damping. The combination was a straightforward application of a classic design equation to a known circuit type.

    Furthermore, a POSITA would have been motivated to incorporate Wong's teachings for several reasons. Hibino explicitly taught using MOSFETs, establishing the circuit in the MOS domain. A POSITA would then seek to fabricate other components, like the snubber capacitor, using the same cost-effective and space-saving MOS process. Wong provided a known solution for creating MOS capacitors suitable for the high-voltage applications described in Hibino. This integration onto a single chip or package was a predictable and desirable design choice to reduce cost, size, and complexity.

  • Expectation of Success: A POSITA would have had a high expectation of success. The combination involved applying established mathematical formulas for circuit design (McMurray) and using standard, well-understood MOS fabrication techniques (Wong) with conventional circuit components (Hibino). The results of such a combination were considered highly predictable.

4. Key Claim Construction Positions

• "dissipative element": Petitioner argued this term should be construed under 35 U.S.C. §112(f) as a means-plus-function element.
  • • Function: "dissipating energy"
  • • Structure: a "resistor"
  • • Alternative: If not construed as a means-plus-function term, Petitioner argued it should still be construed as a "resistor" based on its consistent depiction and description in the specification. This construction is critical because the prior art explicitly discloses a resistor for this function.
• "Voltage spike protection circuitry [...] for voltage-spike-protecting the regulator circuitry": Petitioner argued for the term's plain and ordinary meaning, i.e., "circuitry that protects the regulator circuitry from spikes in voltage."
  • • This position was taken to counter the Patent Owner's narrower construction proposed in parallel litigation, which sought to limit the term to circuitry on the same integrated circuit that protects only against specific types of inductance. Petitioner argued this narrower construction was unsupported and would improperly exclude the prior art.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 5-6, 18-19, 27, and 30 as unpatentable under 35 U.S.C. §103.