PTAB

IPR2017-01124

Intel Corp v. R2 Semiconductor Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Voltage Spike Protection Circuitry for Voltage Regulators
  • Brief Description: The ’250 patent discloses a voltage regulator that includes voltage spike protection circuitry (a "snubber circuit") comprising a dissipative element and a charge-storage circuit. The purported novelty of the invention, distinguished during prosecution, centers on the method for selecting the resistance value of the dissipative element based on the circuit's characteristic impedance and the implementation of the circuit using Metal-Oxide-Semiconductor (MOS) components.

3. Grounds for Unpatentability

Ground 1: Obviousness of the Core Circuit Design - Claims are obvious over Shekhawat in view of McMurray

  • Prior Art Relied Upon: Shekhawat (Patent 7,834,597) and McMurray ("Optimum Snubbers for Power Semiconductors," a 1972 publication).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that the combination of Shekhawat and McMurray rendered the fundamental invention of the ’250 patent obvious. Shekhawat was cited for teaching a voltage regulator with a snubber circuit—containing a resistor and a capacitor—to mitigate voltage spikes. However, Petitioner contended that Shekhawat did not specify how to calculate the optimal value for the snubber resistor. This alleged gap was filled by McMurray, a widely known 1972 publication described as the "classic snubber reference." McMurray taught the precise method for calculating the optimal snubber resistance (R) based on the circuit's parasitic inductance (L) and snubber capacitance (C) using the formula R = 2ζ√(L/C). Petitioner emphasized that this calculation, based on the characteristic impedance (√(L/C)) of a lumped-element approximation of a transmission line, was the very element the Patent Owner added to the claims to overcome prior art rejections during original prosecution.
    • Motivation to Combine: A person of ordinary skill in the art (POSITA) implementing the snubber circuit taught in Shekhawat would have been motivated to optimize its performance to effectively damp voltage spikes. To achieve this, a POSITA would have naturally turned to a foundational and well-established reference like McMurray to apply a standard, predictable, and proven design methodology for selecting the appropriate component values. The motivation was to achieve the known goal of spike reduction using a well-documented technique.
    • Expectation of Success: A POSITA would have had a high expectation of success. The combination involved applying a standard mathematical design principle from McMurray to a conventional circuit topology from Shekhawat, which would have predictably resulted in an effective snubber circuit.

Ground 2: Obviousness of the MOS Implementation - Claims 5-6, 18-19, 27, and 30 are obvious over Shekhawat in view of McMurray and in further view of Wong

  • Prior Art Relied Upon: Shekhawat (Patent 7,834,597), McMurray (1972 publication), and Wong (Patent 5,485,292).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground addressed the claims requiring MOS-specific features. Building on the foundation of Shekhawat and McMurray, Petitioner introduced Wong to teach the limitations related to MOS structures. The challenged claims require, for example, a charge-storage circuit comprising a plurality of series-connected MOS capacitors. Petitioner noted that Shekhawat explicitly taught that its transistors could be implemented as MOSFETs, a primary MOS technology. Wong was cited for teaching the fabrication of high-voltage capacitors using standard MOS technology, specifically disclosing a structure with a plurality of series-connected MOS capacitors. This series connection in Wong was designed to allow the overall capacitor to withstand high voltages while ensuring the voltage across each individual capacitor remained below its breakdown threshold.
    • Motivation to Combine: A POSITA implementing Shekhawat's circuit with MOS transistors (as Shekhawat itself suggested) would be strongly motivated to fabricate the other circuit components, including the snubber capacitor, on the same integrated circuit die using the same MOS process. This common practice reduces manufacturing complexity, size, and cost. Wong provided a known, off-the-shelf solution for creating a high-voltage-tolerant MOS capacitor suitable for Shekhawat’s regulator application. The rationale for series connection in Wong—to divide a high voltage across multiple components—directly mirrored the rationale described in the ’250 patent.
    • Expectation of Success: Integrating Wong's well-understood MOS capacitor design into the circuit established by Shekhawat and McMurray represented a straightforward application of known design and integration techniques. A POSITA would have expected this combination to work predictably to achieve the desired benefits in circuit performance, cost, and size.

4. Key Claim Construction Positions

  • Petitioner argued that the term “dissipative element” should be construed as a means-plus-function term under 35 U.S.C. §112(f). The claimed function is "dissipating energy," and the only corresponding structure disclosed in the ’250 patent's specification is a "resistor." Alternatively, if not a means-plus-function term, its broadest reasonable construction is still "resistor," based on the specification's consistent use of the "Rsp" identifier and standard resistor schematic symbols. This construction was presented as critical to the invalidity case, as it prevents the Patent Owner from broadening the claim scope to argue that other components, such as a capacitor with parasitic resistance, could satisfy the limitation.

5. Relief Requested

  • Petitioner requests institution of inter partes review and cancellation of claims 5-6, 18-19, 27, and 30 of Patent 8,233,250 as unpatentable.