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IPR2017-01184

Advanced Micro Devices Inc v. Broadcom Corp

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1. Case Identification

2. Patent Overview

  • Title: System and method for decoding context adaptive binary arithmetic coded data
  • Brief Description: The ’151 patent discloses a decoder circuit for implementing the H.264 video decoding standard. The invention purports to reduce cost by dividing the decoding process between two components operating at different speeds: a first decoder operating at a slower, average "channel rate" and a second decoder operating at a faster, bursty "consumption rate," with a buffer positioned between them to manage the data flow.

3. Grounds for Unpatentability

Ground 1: Claims 1, 4-6, 8-10, 12, and 14-15 are anticipated by Linzer under 35 U.S.C. §102.

  • Prior Art Relied Upon: Linzer (Patent 6,927,710).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Linzer discloses every element of the challenged claims. Linzer teaches a real-time decoder architecture with distinct components operating at two different rates. It discloses a "transcoder" (an arithmetic decoder) that receives a CABAC bitstream from an input buffer and decodes it into a simpler form ("bins") at an average channel rate. These bins are stored in an output buffer and are subsequently read by a "video decoder" (a syntax assembler) that reconstructs video data at a bursty consumption rate determined by in-picture bit usage. This structure, including the two memories (buffers) and two distinct operating rates, allegedly maps directly to the limitations of the independent claims.

Ground 2: Claims 1, 4-15, and 18 are obvious over Linzer in view of the Admitted Prior Art under 35 U.S.C. §103.

  • Prior Art Relied Upon: Linzer (Patent 6,927,710) and the Admitted Prior Art (“APA”) from the ’151 patent’s provisional application (Application # 60/480,415).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Linzer teaches the overall two-rate decoder architecture. The APA, derived from the patent's own provisional application, discloses the implementation details of a conventional H.264 CABAC decoding loop, including a context modeler, arithmetic decoder, syntax assembler, and context RAM. The combination of Linzer's high-level architecture with the APA's detailed disclosure of a conventional decoding loop allegedly renders the claims obvious. Specifically, the APA's decoding loop provides a clear blueprint for the internal workings of Linzer’s "transcoder" block. Dependent claims requiring a context table RAM (claims 11, 18) are met by the APA's disclosure of a context RAM for storing state information.
    • Motivation to Combine: A person of ordinary skill in the art (POSITA) seeking to implement the decoder architecture taught by Linzer would combine it with a well-understood, conventional decoding loop like that disclosed in the APA. This represents a predictable substitution of one known element (APA's conventional loop) for another (Linzer's functional "transcoder" block) to achieve a predictable result.
    • Expectation of Success: A POSITA would have a high expectation of success, as combining a known system architecture with a standard, interoperable component for that system is a routine design choice.

Ground 3: Claims 1, 4-6, 8-10, 12, and 14-15 are obvious over Linzer in view of Karczewicz under §103.

  • Prior Art Relied Upon: Linzer (Patent 6,927,710) and Karczewicz (Patent 6,856,701).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground was presented as an alternative to Ground 2, in the event the APA is not considered prior art. The argument parallels Ground 2, but substitutes Karczewicz for the APA. Karczewicz, like the APA, discloses the detailed implementation of a conventional CABAC decoding loop, including an arithmetic decoder that generates bins and a syntax assembler that converts bins into syntax elements.
    • Motivation to Combine: The motivation is identical to that in Ground 2. A POSITA would look to a known reference like Karczewicz to provide the specific implementation details for the functional blocks described in Linzer's higher-level system architecture. This combination was argued to be nothing more than the application of a known technique (Karczewicz's decoding loop) to a known device (Linzer's decoder) to yield predictable results.
    • Expectation of Success: A POSITA would have expected success for the same reasons as in Ground 2, as this involves integrating standard, well-documented video decoding components.

4. Key Claim Construction Positions

  • "Decoding/To Decode the Bins at a Consumption Rate": Petitioner argued this phrase should be construed as "decoding... at a rate that is different than the channel rate." This construction is central to the patent's purported novelty and the invalidity arguments, as the core of the invention is the separation of the two rates. The Petitioner contended that the specification and the patent's provisional application consistently distinguish between the input "channel rate" and the faster, bursty output "consumption rate."
  • "Syntax Assembler": Petitioner argued this term is not one of art and lacks a plain and ordinary meaning. It proposed that the term should be construed under §112, ¶ 6 as a means-plus-function term for "decoding bins, thereby generating syntax elements," with the corresponding structure being a variable length code (VLC) decoder and its equivalents.
  • "Context Adaptive Binary Arithmetic Coded Data Decoding Loop": Petitioner proposed construing this term as "a CABAC decoder with a feedback path that enables decode of CABAC encoded data into bins based on previously decoded data." This construction emphasizes the recursive, context-dependent nature of the decoding process, which is disclosed in the prior art.

5. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1, 4-15, and 18 of the ’151 patent as unpatentable.