PTAB

IPR2017-01392

Intel Corp v. Alacritech Inc

Log In
Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Fast-Path Apparatus For Receiving Data Corresponding To A TCP Connection
  • Brief Description: The ’241 patent describes a system and method for offloading network protocol processing from a host computer’s main processor to an intelligent network interface card (INIC). The INIC implements a "fast-path" to process packets for established connections directly, bypassing the host's protocol stack, and a "slow-path" where packets are handled by the host processor for new or complex connections.

3. Grounds for Unpatentability

Ground 1: Obviousness over Erickson, Tanenbaum96, and Alteon

  • Claims Challenged: 1-8, 18, 22, and 23 are obvious over the combination of Erickson, Tanenbaum96, and Alteon.
  • Prior Art Relied Upon: Erickson (Patent 5,768,618), Tanenbaum96 (A. Tanenbaum, Computer Networks, 3rd ed., 1996), and Alteon ("Gigabit Ethernet Technical Brief: Achieving End-to-End Performance").
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Erickson disclosed a foundational I/O device adapter that performs fast-path network processing using scripts, primarily for UDP/IP but noting applicability to TCP/IP. To supply the missing TCP-specific details, a person of ordinary skill in the art (POSITA) would look to Tanenbaum96, a standard textbook on the subject. Tanenbaum96 taught using prototype headers and connection records to sort incoming TCP packets into a fast-path (processed on the adapter) or a slow-path (processed by the host), thus disclosing the claimed sorting and processing steps. Petitioner asserted that the final key limitation—processing multiple protocol layer headers "without an interrupt dividing" the processing—was taught by Alteon. Alteon described an intelligent adapter that reduces host processor load by issuing a single interrupt for multiple data packets, thereby teaching the absence of intra-packet interrupts during header validation.
    • Motivation to Combine: Petitioner contended that a POSITA would combine these references because Erickson expressly incorporated an earlier edition of the Tanenbaum textbook, directly motivating consultation of the then-current Tanenbaum96 for implementing TCP functionality. Furthermore, Alteon addressed the same problem Erickson sought to solve—reducing host CPU intervention. A POSITA would be motivated to incorporate Alteon’s single-interrupt strategy into the Erickson/Tanenbaum96 system to further improve performance and reduce host interrupts, which was a well-known goal in the art.
    • Expectation of Success: Petitioner asserted a high expectation of success, as the combination involved implementing the well-documented and standardized TCP/IP protocol on an existing adapter architecture using known techniques for performance enhancement.

Ground 2: Obviousness over Erickson and Tanenbaum96

  • Claims Challenged: 9-17, 19-21, and 24 are obvious over the combination of Erickson and Tanenbaum96.
  • Prior Art Relied Upon: Erickson (Patent 5,768,618) and Tanenbaum96 (A. Tanenbaum, Computer Networks, 3rd ed., 1996).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground primarily addressed the transmit-side claims. Petitioner argued that Erickson disclosed an I/O adapter capable of transmitting data by obtaining data from host memory (via DMA), using a predetermined script, and forming packets using a header template. Tanenbaum96 provided the necessary TCP-specific teachings, including dividing a data stream into multiple "segments" for transmission and using a "prototype header" (analogous to Erickson's template) to prepend headers to each segment for fast-path transmission. Tanenbaum96 further taught that this processing could be performed by a processor on the network interface card itself (the "second processor" of the claims). The combination thereby taught obtaining data, segmenting it, and having an adapter prepend headers to form packets for transmission.
    • Motivation to Combine: The motivation was identical to Ground 1. Erickson’s explicit reference to the Tanenbaum textbook would have prompted a POSITA to consult Tanenbaum96 to adapt Erickson’s UDP-focused disclosure for the widely used TCP protocol.
    • Expectation of Success: The expectation of success was high because it involved applying standard TCP transmission principles from a leading textbook (Tanenbaum96) to a disclosed hardware adapter (Erickson) designed for protocol offloading.

4. Key Claim Construction Positions

Petitioner dedicated significant argument to the indefiniteness of two key claim phrases, asserting they should be construed before assessing obviousness.

  • “[first/second] mechanism”: Petitioner argued this term, used in claims such as 1, 3, and 17, is a nonce word functioning as a means-plus-function limitation under 35 U.S.C. §112(6). Petitioner contended that the specification failed to disclose the corresponding structure or algorithm necessary to perform the claimed functions (e.g., "processing," "sorting," "sending"). At best, the patent implied a "sequencer running microcode," but provided no actual microcode or algorithm. Therefore, Petitioner argued the term was indefinite for failing to disclose adequate corresponding structure.
  • “without an interrupt dividing”: Petitioner argued this phrase, central to claims like 1, 18, and 22, is indefinite. The claims require header validation to occur on the INIC (the "first mechanism") without an interrupt dividing the processing. Petitioner contended that a POSITA would understand interrupts as signals sent to the host processor. Therefore, the phrase described an interrupt on the host processor "dividing" processing that was occurring entirely on the separate INIC, a concept Petitioner argued was technically nonsensical and would not have been understood by a POSITA.

5. Relief Requested

  • Petitioner requested the institution of an inter partes review and the cancellation of claims 1-24 of the ’241 patent as unpatentable.