PTAB

IPR2017-01395

Intel Corp v. Alacritech Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Intelligent Network Interface System and Method for Protocol Processing
  • Brief Description: The ’948 patent discloses a system for offloading Transmission Control Protocol (TCP) processing from a host computer to an intelligent network interface card (NIC). The NIC uses a dual-mode approach: a "fast path" on the NIC hardware processes normal packets to bypass the host's protocol stack, while a "slow path" routes packets with exception conditions to the host's protocol stack for conventional processing.

3. Grounds for Unpatentability

Ground 1: Obviousness over Thia, Tanenbaum96, and Stevens2 - Claims 1, 3, 6-9, 11, 14-17, 19, and 21-22 are obvious over Thia in view of Tanenbaum96 and Stevens2.

  • Prior Art Relied Upon:
    • Thia (Y.H. Thia & C.M. Woodside, "A Reduced Operation Protocol Engine (ROPE) for a Multiple-Layer Bypass Architecture," 1995).
    • Tanenbaum96 (Andrew S. Tanenbaum, "Computer Networks, 3rd ed.," 1996).
    • Stevens2 (Gary R. Wright & W. Richard Stevens, "TCP/IP Illustrated: The Implementation," 1995).
  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued that the prior art combination taught all limitations of the challenged claims. Thia disclosed a general hardware-based protocol offload engine (a "ROPE" chip on a NIC) that implements a fast path/slow path architecture for a generic Open Systems Interconnect (OSI) protocol stack. Thia’s system used a "receive bypass test" on the NIC to determine if an incoming packet was "normal" and eligible for fast-path processing, which bypassed the host's Standard Protocol Stack (SPS). Packets failing the test were sent to the host's SPS for slow-path processing. Thia also disclosed using Direct Memory Access (DMA) to transfer the processed payload data to host memory.

      Petitioner asserted that Tanenbaum96, a standard textbook, taught the specifics of the dominant TCP/IP protocol, including the well-known "Header Prediction" algorithm for fast-path processing. This algorithm checks if a packet is "normal" by verifying the connection is in the ESTABLISHED state, the packet is not fragmented, no special flags (like SYN, FIN, or RST) are set, and it is in the correct sequence. Packets meeting these criteria are processed on a fast path, bypassing the main protocol stack. Stevens2 provided a detailed analysis of the widely used BSD source code implementation of Jacobson's Header Prediction, confirming the exact conditions taught in Tanenbaum96.

      The combination allegedly rendered the claims obvious because it would have been a simple design choice to implement Thia's generalized hardware offload architecture using the specific, well-known TCP/IP Header Prediction rules from Tanenbaum96 and Stevens2. Independent claims 1, 9, and 17 were met by this combination, as the NIC in Thia performs the "checking" for exception conditions (as defined by Tanenbaum96/Stevens2) and either bypasses the host stack for normal packets or directs exception packets to it. The dependent claims merely added conventional features, such as using DMA (taught by Thia), comparing IP addresses and TCP ports (an explicit step in Header Prediction taught by Tanenbaum96), and identifying specific TCP flags like RST and SYN as exception conditions (also explicitly part of Header Prediction taught by Tanenbaum96 and Stevens2).

    • Motivation to Combine: Petitioner argued a person of ordinary skill in the art (POSITA) would combine these references to improve network performance, a recognized goal in the art. Thia explicitly stated its hardware offload architecture could be used with "any standard protocol." By 1996, TCP/IP had become the dominant protocol, making it an obvious choice for implementation. A POSITA seeking to apply Thia's concepts to TCP/IP would naturally have consulted standard, authoritative textbooks like Tanenbaum96 and Stevens2 to learn the established rules for TCP/IP fast-path processing, namely the Header Prediction algorithm. The motivation was to achieve the benefits of hardware offload described in Thia (reduced host CPU load, eliminated data copying) for the most prevalent networking protocol.

    • Expectation of Success: A POSITA would have had a high expectation of success. The combination involved applying a specific, well-documented software algorithm (Header Prediction) to a compatible and generalized hardware offload architecture (Thia's ROPE). The references addressed the same problem of protocol processing bottlenecks and proposed similar fast-path solutions, making their integration straightforward and predictable.

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1, 3, 6-9, 11, 14-17, 19, and 21-22 of Patent 8,805,948 as unpatentable.