PTAB

IPR2017-01405

Intel Corp v. Alacritech Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Network Interface Device That Fast-Path Processes Solicited Session Layer Read Commands
  • Brief Description: The ’205 patent describes a network interface device designed to accelerate data transfers by offloading protocol processing from a host computer. The system uses a "fast-path" to bypass the host's conventional protocol stack for expected data packets, thereby reducing the host CPU's workload.

3. Grounds for Unpatentability

Ground 1: Obviousness over Thia and Satran - Claims 3, 9-10, 16, 22, 27-33, and 35-36 are obvious over Thia in view of Satran.

  • Prior Art Relied Upon: Thia (a 1995 journal article, “A Reduced Operation Protocol Engine (ROPE) for a multiple-layer bypass architecture”) and Satran (two 2000 Internet Drafts defining SCSI over TCP and iSCSI, collectively).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Thia disclosed the core architecture of the challenged claims. Thia taught a network interface device, comprising a Reduced Operation Protocol Engine (ROPE) chip and a Network Interface Adapter (NIA), that performs fast-path processing. This system uses a "bypass test" on incoming packets; if a packet's header matches a predicted template, it is processed on the ROPE chip's "bypass stack," avoiding the host computer's standard multi-layer protocol stack (SPS). This bypass handles all relevant protocol processing, including network and transport layers. Satran was argued to supply the missing session-layer protocol, disclosing the iSCSI protocol which uses READ commands to transfer data from network storage devices. Petitioner contended that iSCSI operates at the session layer within the OSI model, a fact acknowledged by the ’205 patent itself. The combination, therefore, taught applying Thia's fast-path bypass architecture to session-layer iSCSI READ commands.
    • Motivation to Combine: A POSITA would combine Thia and Satran for several reasons. First, it would provide Thia’s conceptual bypass system with a real-world, well-known communications protocol (iSCSI), making it practical. Second, adding iSCSI functionality would improve Thia's operation and broaden its market appeal. Third, iSCSI is inherently a network protocol designed for the type of network environment in which Thia operates. Finally, using iSCSI provides known benefits like easier sharing of network-attached devices and reduced host workload, which aligns with the overall goal of Thia's architecture.
    • Expectation of Success: Petitioner asserted a POSITA would have had a high expectation of success. Both Thia’s architecture and the iSCSI protocol were described in the context of the OSI networking model, making their integration conceptually straightforward. Furthermore, Thia expressly stated its design allows for easy adaptation and migration from existing systems and protocols, indicating it was designed for exactly this type of combination.

Ground 2: Obviousness over Thia, Satran, and Carmichael - Claims 24-26 are obvious over Thia in view of Satran and Carmichael.

  • Prior Art Relied Upon: Thia (1995 journal article), Satran (2000 Internet Drafts), and Carmichael (Patent 5,894,560).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon the combination of Thia and Satran and added Carmichael to teach limitations specific to claims 24-26. These claims require that the iSCSI read request passed from the host to the network interface device be "accompanied by an indication of where the destination memory is located." Claim 26 further required this indication to be passed before the response data is received. While Thia taught using DMA to move data to host memory, Carmichael specifically taught an efficient method for managing such transfers. Carmichael disclosed using a Physical Region Descriptor (PRD) table and scatter-gather lists as the "indication" to specify memory locations for incoming data. Critically, Carmichael's process flow showed that the CPU issues the "start scatter-gather command" to the I/O controller before the data transfer occurs, directly mapping to the limitations of claims 24-26.
    • Motivation to Combine: A POSITA would combine Carmichael with the Thia/Satran system to enhance its efficiency. The base combination already involved offloading storage commands (iSCSI) and using DMA for data transfer. Carmichael was directed at improving the efficiency of I/O and DMA performance at minimal cost. A POSITA would have recognized that incorporating Carmichael's scatter-gather list method into Thia's DMA engine was a logical next step to optimize the data transfer process, a known design goal in the field.
    • Expectation of Success: The combination was predictable. Carmichael was designed to be compatible with various operating systems and storage protocols, as long as the devices were capable of DMA transfers, which Thia's system was. Integrating a known DMA optimization technique (Carmichael) into a system that already used DMA (Thia) would have been a straightforward engineering task with a predictable result: more efficient data handling.

4. Key Claim Construction Positions

  • "means... for" [performing fast-path and slow-path processing] (Claim 31): Petitioner argued this term, recited in claim 31, rendered the claim indefinite under 35 U.S.C. §112, ¶6. The claim required a single "means" to perform four functions: (1) receiving a response, (2) fast-path processing it, (3) receiving a subsequent portion, and (4) slow-path processing the subsequent portion. Petitioner contended that the ’205 patent disclosed the network adapter as the structure for fast-path processing but disclosed the host computer as the structure for slow-path processing. Because the patent allegedly failed to disclose a single structure coupled to the host that could perform both fast-path and slow-path processing, the claim lacked sufficient corresponding structure and was indefinite.

5. Key Technical Contentions (Beyond Claim Construction)

  • Priority Date of iSCSI-related Claims: A central contention was that the challenged claims (3, 9-10, 16, 22, 24-33, and 35-36) were not entitled to the patent's earliest claimed priority date of 1997. Petitioner argued that because these claims all depend on or recite iSCSI limitations, their priority date could be no earlier than September 29, 2000. This was the filing date of the first application in the patent's chain of priority that, according to the patent's own prosecution history, provided adequate written description for the iSCSI technology. This later priority date was critical for establishing that the Satran references, published in 2000, qualify as prior art against these specific claims.

6. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 3, 9-10, 16, 22, 24-33, and 35-36 of the ’205 patent as unpatentable.