Samsung Electronics Co., Ltd. v. ProMOS Technologies, Inc.

1. Case Identification

• Patent #: 6,208,574
• Filed: May 12, 2017
• Petitioner(s): Samsung Electronics Co., Ltd.
• Patent Owner(s): Promos Technologies, Inc.
• Challenged Claims: 1-3, 30-37

2. Patent Overview

• Title: Sense Amplifier for High-Density Integrated Circuit Memory
• Brief Description: The ’574 patent relates to a sense amplifier for a high-density integrated circuit memory using CMOS technology. The invention focuses on the architecture of local sense amplifiers, write driver circuits, and read amplifiers within a memory array organized by columns.

3. Grounds for Unpatentability

Ground 1: Obviousness over Inoue, Min, and Hamade - Claims 1-3 and 30-37 are obvious over Inoue, Min, and Hamade.

• Prior Art Relied Upon: Inoue (Japanese Patent Publication JPS58-128087), Min (UK Patent Application Publication No. G.B. 2246005A), and Hamade (Patent 5,323,349).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that the challenged claims are obvious over a combination of three prior art references from the same field of semiconductor memory.
    • Inoue was asserted to disclose the fundamental building block: a sense amplifier with a flip-flop latch circuit (FIG. 6) for a single column in a dynamic memory. This circuit includes internal nodes corresponding to bit lines and the core P-channel and N-channel transistors forming the latch.
    • Min was introduced to teach the replication of Inoue's single-column sense amplifier across multiple columns. Min discloses a memory device with a plurality of sense amplifiers (SA1-SAN), each coupled to a respective bit line pair, and teaches using common driver signals for these columns. Petitioner contended this provides the blueprint for creating the claimed "plurality of sense amplifiers."
    • Hamade was asserted to supply the final key element missing from the Inoue-Min combination: a dedicated high-speed read circuit. Hamade discloses a "drive circuit 9" for each bit line pair that functions as a "column read amplifier," amplifying potentials from the bit lines to enable fast read operations. This circuit is provided for each column in Hamade's memory device.
  • Motivation to Combine: Petitioner argued a person of ordinary skill in the art (POSITA) would be motivated to combine these references for predictable results. A POSITA would combine Inoue's single-column sense amplifier with Min's multi-column architecture to create a practical and scalable DRAM, as it was well-known that such memories contained thousands of columns. This combination, however, would lack efficient read circuitry. A POSITA would then look to other art in the same field, like Hamade, to find a solution. Hamade's disclosure of a local column read amplifier for each column provided a known solution to improve read speed, motivating its integration into the Inoue-Min system to create a complete, high-performance memory device.
  • Expectation of Success: A POSITA would have had a reasonable expectation of success in making this combination. The integration involved applying known design principles—replicating a circuit for a multi-column array (Inoue and Min) and adding a dedicated read amplifier for performance (Hamade)—that were common in the field of semiconductor memory design. The combination of these familiar elements would predictably yield a functional DRAM with the claimed features.

4. Key Claim Construction Positions

Petitioner asserted that specific claim terms containing the word "local" are central to the invalidity analysis and proposed the following constructions based on the intrinsic record, including prosecution history disavowal.

• "local data write driver circuit": Petitioner proposed this term, found in independent claims 1, 4, and 30, be construed as "a data write driver circuit that is associated with only one latch circuit."
• "local column read amplifier": Similarly, Petitioner proposed this term be construed as "a column read amplifier that is associated with only one latch circuit."
• "local sense amplifier drive transistor(s)": This term from independent claim 1 was proposed to be construed as "sense amplifier drive transistor(s) associated with only one latch circuit."

Petitioner's rationale for these constructions was consistent across all three terms. It argued that the plain language of the claims links each "local" component to a single corresponding sense amplifier, which itself contains a single latch circuit. Furthermore, Petitioner contended that during prosecution of a related patent, the patentee explicitly distinguished "local" from "global" by defining "local" as being associated with only one sense amplifier, thereby disavowing a broader scope.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-3 and 30-37 of the ’574 patent as unpatentable.