PTAB

IPR2017-01415

Samsung Electronics Co Ltd v. ProMOS Technologies Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Sense Amplifier for High-Density Integrated Circuit Memory
  • Brief Description: The ’574 patent relates to a sense amplifier circuit for a high-density integrated circuit memory, such as a Dynamic Random Access Memory (DRAM), using CMOS technology. The invention discloses a sense amplifier architecture that includes local data write driver circuits and local column read amplifiers associated with individual latch circuits.

3. Grounds for Unpatentability

Ground 1: Obviousness over Inoue, Min, and Hamade - Claims 4-10, 14-16, and 21-27 are obvious over Inoue in view of Min and Hamade.

  • Prior Art Relied Upon: Inoue (Japanese Patent Publication JPS58-128087), Min (UK Patent Application G.B. 2246005A), and Hamade (Patent 5,323,349).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that the combination of these references disclosed all limitations of independent claim 4 and its dependents. Inoue taught the fundamental sense amplifier with a flip-flop (latch) circuit for a dynamic memory. However, Inoue only showed a single sense amplifier. Min addressed this by teaching the replication of sense amplifiers into a multi-column memory architecture, where each sense amplifier is coupled to a respective pair of bit lines. This Inoue-Min combination, however, lacked specific circuitry for high-speed read operations. Hamade was argued to supply this missing element by disclosing a "local column read amplifier" (drive circuit 9) associated with each sense amplifier latch to amplify and read data from the bit lines. Hamade also disclosed local data write driver circuits.
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine Inoue and Min to scale Inoue’s single sense amplifier into a practical, multi-column DRAM, a well-known design objective. A POSITA would then look to Hamade to add the necessary read circuitry that was absent from the Inoue-Min combination. The motivation was to create a fully functional, high-speed DRAM by integrating known solutions for amplification (Inoue), multi-column architecture (Min), and high-speed data reading (Hamade).
    • Expectation of Success: A POSITA would have had a reasonable expectation of success because all three references operate in the same field of semiconductor memory and address complementary aspects of DRAM design. The combination involved applying known design principles (replication of circuits for multiple columns) and integrating standard functional blocks (read amplifiers) to yield a predictable result.

Ground 2: Obviousness over Inoue, Min, Hamade, and Ogawa - Claims 11-13 are obvious over Inoue in view of Min, Hamade, and Ogawa.

  • Prior Art Relied Upon: Inoue (Japanese Patent Publication JPS58-128087), Min (UK Patent Application G.B. 2246005A), Hamade (Patent 5,323,349), and Ogawa (Patent 5,293,347).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground built upon the combination in Ground 1 to address the limitations of claims 11-13, which required the write control signal to be a "column write signal," specifically a "decoded column write signal." While the base combination disclosed a write control signal (clock ϕ2 in Inoue), it did not specify that this signal was a decoded signal for selecting a particular column. Petitioner asserted that Ogawa taught this feature, disclosing a column decoder that generates a signal to select a desired bit line pair (column) for a write operation by activating the appropriate pass transistors.
    • Motivation to Combine: A POSITA, having already combined Inoue, Min, and Hamade to create a multi-column memory array, would be motivated to incorporate Ogawa’s teachings to implement an essential feature: the ability to select and write to a specific column. Ogawa provided a known method for column selection in DRAMs. This modification was necessary to make the combined memory array operable, as it would otherwise lack a mechanism to direct write operations to a specific column.
    • Expectation of Success: Implementing a column decoder as taught by Ogawa to control the pass transistors in the Inoue-based circuit was a standard and predictable design choice for a multi-column DRAM. The integration would allow for the selective writing of data, a fundamental requirement for memory operation, and thus would have been a straightforward modification for a POSITA.

  • Additional Grounds: Petitioner asserted that claim 17 is obvious over Inoue, Min, and Hamade, and that claim 18 is obvious over Inoue, Min, Hamade, and Ogawa, relying on similar combination rationales focused on specific dependent claim features.

4. Key Claim Construction Positions

  • "local data write driver circuit": Petitioner proposed this term be construed as "a data write driver circuit that is associated with only one latch circuit." This construction was argued to be critical for distinguishing the claimed invention from prior art with "global" write circuits shared among multiple sense amplifiers. Petitioner contended that the specification, claims, and prosecution history (including disavowal in a related patent) supported this narrow interpretation of "local."
  • "local column read amplifier": Similarly, Petitioner proposed this term be construed as "a column read amplifier that is associated with only one latch circuit." The rationale followed that for the "local data write driver circuit," emphasizing the one-to-one correspondence between the amplifier and the latch circuit as a key feature of the invention, distinguishing it from architectures using shared or global components.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 4-18 and 21-27 of the ’574 patent as unpatentable.