PTAB

IPR2017-01415

Samsung Electronics Co., Ltd. v. ProMOS Technologies, Inc.

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1. Case Identification

2. Patent Overview

  • Title: Sense Amplifier for Integrated Circuit Memory
  • Brief Description: The ’574 patent relates to a sense amplifier for a very high-density integrated circuit memory, such as a Dynamic Random Access Memory (DRAM), using CMOS technology. The invention aims to provide improved sense amplifier arrangements with local write driver and read amplifier circuits.

3. Grounds for Unpatentability

Ground 1: Obviousness over Inoue, Min, and Hamade - Claims 4-10, 14-16, and 21-27 are obvious over Inoue in view of Min and Hamade.

  • Prior Art Relied Upon: Inoue (Japanese Patent Publication JPS58-128087), Min (UK Patent Application G.B. 2246005A), and Hamade (Patent 5,323,349).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that the combination of these references taught all elements of the challenged claims. Independent claim 4 recites a sense amplifier arrangement for an integrated circuit memory with a plurality of sense amplifiers, each having a latch circuit. Petitioner asserted that Inoue disclosed the fundamental sense amplifier with a flip-flop latch circuit. However, Inoue only showed a single sense amplifier. Min was introduced to teach the replication of sense amplifiers into a multi-column memory array, a common practice for creating practical DRAMs. The combined Inoue-Min system, however, lacked a local column read amplifier. Hamade was introduced to supply this missing element, as it disclosed a drive circuit for each bit line pair that functioned as a local column read amplifier, associated with a single latch circuit. Furthermore, Petitioner contended that the local data write driver circuits recited in claim 4 were taught by the write circuits disclosed in Inoue (transistors QN6, QN8, QN7, QN9), which are local to a single latch.
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine Inoue and Min to implement Inoue's efficient sense amplifier design in a practical, multi-column DRAM, which Min explicitly teaches. A POSITA would then incorporate Hamade's read amplifier circuitry into the Inoue-Min system to add the necessary and advantageous capability of high-speed data reading, which was missing from the Inoue-Min combination but essential for a functional DRAM.
    • Expectation of Success: A POSITA would have a reasonable expectation of success because all three references are in the same field of semiconductor memory design. Combining these known elements (sense amplifiers, multi-column arrays, read amplifiers) using established methods would predictably result in an improved DRAM with faster read operations.

Ground 2: Obviousness over Inoue, Min, Hamade, and Ogawa - Claims 11-13 are obvious over the combination of Inoue, Min, and Hamade in view of Ogawa.

  • Prior Art Relied Upon: Inoue (Japanese Patent Publication JPS58-128087), Min (UK Patent Application G.B. 2246005A), Hamade (Patent 5,323,349), and Ogawa (Patent 5,293,347).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground builds on the Inoue-Min-Hamade combination from Ground 1 and adds Ogawa to teach limitations in claims 11-13. Claim 11 requires that the "write control signal is a column write signal." Petitioner argued that while the primary combination disclosed a write control signal (Inoue's clock ϕ2), it did not explicitly teach that this signal was a column-specific write signal. Ogawa was introduced to remedy this, as it explicitly taught using a column decoder to generate a decoded column write signal to select a desired bit line pair (i.e., a column) for a write operation.
    • Motivation to Combine: A POSITA would be motivated to integrate Ogawa's column decoding scheme into the Inoue-Min-Hamade system to refine its operation. This addition was a necessary feature to enable the selection of a specific column of memory cells for writing in a large-scale DRAM, providing a clear benefit and making the overall design more practical and functional.
    • Expectation of Success: The combination was presented as predictable. A POSITA would know how to use a standard column decoder, as taught by Ogawa, to drive the pass transistors of the sense amplifiers in the Inoue-Min-Hamade system to achieve the predictable result of column-selective writing.

  • Additional Grounds: Petitioner asserted that claim 17 is obvious over Inoue, Min, and Hamade, and claim 18 is obvious over Inoue, Min, Hamade, and Ogawa. These grounds relied on the same core combinations but focused on specific dependent claim limitations, such as the use of complementary signals for writing data into an active memory block (claim 17) and controlling data write signals to have the same value when no write is to occur (claim 18), with Ogawa again providing the specific control logic.

4. Key Claim Construction Positions

  • “local data write driver circuit”: Petitioner argued this term should be construed as “a data write driver circuit that is associated with only one latch circuit.” This construction was asserted to be supported by the claims, specification, and prosecution history of a related patent, where the patentee distinguished "local" (associated with one sense amplifier/latch) from "global" (connected to several). This construction is critical for mapping Inoue's write circuits, which are each tied to a single flip-flop, to the claim language.
  • “local column read amplifier”: Similarly, Petitioner proposed this term be construed as “a column read amplifier that is associated with only one latch circuit.” The reasoning mirrors the argument for the write driver circuit, relying on the plain language of the claims and the patent's intrinsic distinction between local and global components. This construction was vital to arguing that Hamade’s per-column drive circuit met the "local" limitation.

5. Relief Requested

  • Petitioner requested the institution of an inter partes review and the cancellation of claims 4-18 and 21-27 of the ’574 patent as unpatentable.