PTAB

IPR2017-01418

Samsung Electronics Co Ltd v. ProMOS Technologies Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Method for Manufacturing a Semiconductor Device
  • Brief Description: The ’044 patent discloses methods for forming electrical contacts in a semiconductor device. The invention is directed to a dual-damascene-like process for simultaneously forming a contact hole to a gate electrode and another contact hole to a source/drain region in the substrate.

3. Grounds for Unpatentability

Ground 1: Obviousness over Fujimoto, Yaung, and Ho - Claims 1-4, 6-8, and 12-14 are obvious over Fujimoto in view of Yaung and Ho.

  • Prior Art Relied Upon: Fujimoto (Patent 6,399,470), Yaung (Patent 6,165,880), and Ho (Patent 6,620,733).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Fujimoto taught the core method of manufacturing a semiconductor device claimed in independent claim 1. This included providing active devices (MOS transistors) on a substrate, each with a stacked gate structure comprising a gate electrode (polysilicon), a silicide layer over the electrode, a protective cap layer, and diffused source/drain regions. Fujimoto also disclosed depositing a dielectric layer, forming a first opening to expose the silicide of one device, depositing a second dielectric layer, and then forming second and third openings. Petitioner contended that Yaung, which addresses similar fabrication processes, supplied elements not explicit in Fujimoto, such as using a conventional photoresist for an etch mask and forming a gate oxide under the polysilicon gate. To address the second masking step, Petitioner asserted that Ho taught a sophisticated multi-layer mask structure—including a hardmask, a bottom anti-reflective coating (BARC), and a second photoresist—which was ideal for the complex etching required by Fujimoto. Dependent claims were allegedly met by explicit teachings or obvious modifications, such as sharing a diffused region (claim 2) or using BPSG for the dielectric (claim 3, taught by Yaung).
    • Motivation to Combine: A POSITA would combine Fujimoto and Yaung because both relate to forming contacts in transistors, and Yaung provided well-known details (e.g., using a photoresist mask) where Fujimoto was silent. A POSITA would further incorporate Ho's advanced multi-layer mask because Fujimoto’s process requires etching contact holes to different depths to reach both the gate and substrate. Ho’s hardmask structure was a known solution for improving etch selectivity and critical dimension control in such applications, a predictable improvement over a simple photoresist mask.
    • Expectation of Success: Petitioner argued that combining these known semiconductor fabrication techniques was routine. A POSITA would have reasonably expected that integrating Yaung’s standard photoresist process and Ho’s advanced hardmask structure into Fujimoto’s general framework would successfully create the desired contact openings with improved precision.

Ground 2: Obviousness over Fujimoto, Yaung, Ho, and Paterson - Claim 5 is obvious over the combination for Ground 1 in view of Paterson.

  • Prior Art Relied Upon: Fujimoto (Patent 6,399,470), Yaung (Patent 6,165,880), Ho (Patent 6,620,733), and Paterson (Patent 5,108,941).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground challenged claim 5, which specifies that the etching step for the first opening comprises a "wet etch." The primary combination of Fujimoto, Yaung, and Ho taught a dry etch process. Petitioner argued that Paterson explicitly disclosed using either "conventional wet or plasma etches" for forming a via through a dielectric layer to expose an underlying silicide film. This process in Paterson was alleged to be analogous to forming the first opening in Fujimoto.
    • Motivation to Combine: A POSITA, when implementing the Fujimoto/Yaung/Ho process, would have recognized that the choice between wet and dry etching for forming the contact opening was a well-known design choice. Paterson taught that both were viable options, with the selection depending on factors like the specific dielectric material used. Therefore, it would have been obvious to substitute the dry etch taught in the primary combination with a wet etch as taught by Paterson to achieve the same result of creating an opening.
    • Expectation of Success: The substitution of one known etching technique for another (wet vs. dry) was a routine and predictable modification in semiconductor manufacturing. A POSITA would have expected a wet etch to successfully form the required opening in the dielectric layer.

Ground 3: Obviousness over Fujimoto, Yaung, Ho, and Ohkawa - Claim 15 is obvious over the combination for Ground 1 in view of Ohkawa.

  • Prior Art Relied Upon: Fujimoto (Patent 6,399,470), Yaung (Patent 6,165,880), Ho (Patent 6,620,733), and Ohkawa (Patent 6,091,154).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground targeted claim 15, which required the step of forming the second and third openings to comprise a "self-aligned contact step." While Fujimoto disclosed a process for forming these contacts, it explicitly stated it was not a self-aligned contact (SAC) process. Petitioner argued that Ohkawa taught a similar fabrication method but specifically disclosed forming contact holes to both the substrate and a gate wiring layer using a SAC method.
    • Motivation to Combine: A POSITA would have been motivated to modify the Fujimoto/Yaung/Ho process to include Ohkawa’s SAC step because the benefits of SAC were well-known. Both Ohkawa and Fujimoto recognized that a SAC process provides higher tolerance to mask misalignment, allowing for finer device features and greater manufacturing accuracy. Since Fujimoto’s non-SAC method was susceptible to misalignment issues, incorporating Ohkawa's known SAC technique was an obvious way to improve the process and achieve a predictable increase in device density and reliability.
    • Expectation of Success: Applying a known SAC technique, as taught by Ohkawa, to the fabrication process of Fujimoto was a straightforward application of a known solution to improve a known device. A POSITA would have reasonably expected this combination to yield a workable process with the known benefits of self-alignment.

  • Additional Grounds: Petitioner asserted additional obviousness challenges, including combinations incorporating Sonego (Patent 6,156,637) to teach rapid thermal annealing for planarization (Grounds 3 and 6), and various permutations of the primary references to address the remaining claims (Grounds 4, 5, and 8).

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-23 of the ’044 patent as unpatentable.