PTAB

IPR2017-01418

Samsung Electronics Co., Ltd. v. ProMOS Technologies, Inc.

Log In

1. Case Identification

2. Patent Overview

  • Title: Method for Manufacturing a Semiconductor Device
  • Brief Description: The ’044 patent discloses methods for forming electrical contacts in a semiconductor device. The invention is directed at a multi-step process for creating contact holes through various deposited layers to connect with underlying active device structures, such as gate electrodes and diffused regions in a substrate.

3. Grounds for Unpatentability

Ground 1: Claims 1-4, 6-8, and 12-14 are obvious over Fujimoto, Yaung, and Ho.

  • Prior Art Relied Upon: Fujimoto (Patent 6,399,470), Yaung (Patent 6,165,880), and Ho (Patent 6,620,733).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that the combination of Fujimoto, Yaung, and Ho teaches every limitation of the challenged claims. Fujimoto was asserted to disclose the fundamental method of manufacturing a semiconductor device with at least two active devices, each comprising a gate electrode stack (polysilicon, silicide, cap), spaced-apart diffused regions, and subsequent deposition of dielectric layers. While Fujimoto teaches MOS transistors, Petitioner supplemented its disclosure with Yaung to explicitly teach forming a gate oxide under the polysilicon gate electrode. For the limitations requiring a second mask and photoresist, Petitioner relied on Ho, which teaches a sophisticated multi-layer etching mask structure—comprising a hardmask, a bottom anti-reflective coating (BARC), and a photoresist—used for similar semiconductor etching processes.
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine Fujimoto with Yaung’s teaching of a gate oxide to ensure the proper, fundamental operation of the disclosed MOS transistors. A POSITA would further be motivated to incorporate Ho’s detailed mask structure into the process of Fujimoto and Yaung to improve the etching of deep, high-aspect-ratio contact holes. Ho’s structure was known to enhance etch selectivity and maintain critical dimensions, addressing a known challenge in the art.
    • Expectation of Success: Petitioner asserted that a POSITA would have had a high expectation of success. The combination involved applying known, conventional process steps (like adding a gate oxide or using an advanced mask) from Yaung and Ho to the base process of Fujimoto to achieve their well-understood functions and predictable results.

Ground 2: Claim 5 is obvious over Fujimoto, Yaung, Ho, and Paterson.

  • Prior Art Relied Upon: Fujimoto (Patent 6,399,470), Yaung (Patent 6,165,880), Ho (Patent 6,620,733), and Paterson (Patent 5,108,941).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground specifically addresses claim 5, which depends from claim 1 and requires the etching step for the first opening to comprise a "wet etch." The primary combination of Fujimoto, Yaung, and Ho discloses a dry etch process. Petitioner introduced Paterson, which teaches fabricating multilevel dielectric structures and explicitly discloses that etching vias can be performed by "conventional wet or plasma etches."
    • Motivation to Combine: A POSITA would have viewed wet etching and dry (plasma) etching as a finite number of known, predictable alternatives for removing a dielectric layer. Paterson explicitly presents this choice. Therefore, a POSITA would have been motivated to substitute the dry etch taught in the primary combination with the wet etch taught by Paterson as a simple design choice, depending on the specific materials and desired etch profile.
    • Expectation of Success: The substitution of one well-known etching technique for another would have predictably resulted in the formation of the desired contact opening.

Ground 3: Claims 9-11 are obvious over Fujimoto, Yaung, Ho, and Sonego.

  • Prior Art Relied Upon: Fujimoto (Patent 6,399,470), Yaung (Patent 6,165,880), Ho (Patent 6,620,733), and Sonego (Patent 6,156,673).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground targets claims 9-11, which require "rapid thermal annealing to reflow the second layer of dielectric material to obtain a substantially planar surface." While Fujimoto teaches a generic "flattening process" for this layer, it does not specify the technique. Petitioner introduced Sonego, which is also directed to semiconductor manufacturing and explicitly discloses a thermal reflowing operation using rapid thermal annealing to "optimiz[e] the planarity" of a dielectric layer. Sonego further teaches performing this annealing in the 900°C to 1000°C range, overlapping the ranges in claims 10 and 11.
    • Motivation to Combine: A POSITA, faced with implementing Fujimoto's general instruction to "flatten" the dielectric layer, would have been motivated to look to known planarization techniques. Sonego provides a specific, known solution (rapid thermal annealing) for the exact same problem in a similar technological context.
    • Expectation of Success: Applying the known rapid thermal annealing process from Sonego to the device in Fujimoto to achieve planarization would have been a straightforward application of a known technique to yield a predictable result.

  • Additional Grounds: Petitioner asserted additional obviousness challenges, including grounds combining Fujimoto and Ho (for claims 16, 19, 22); Fujimoto, Ho, and Yaung (for claims 17, 18, 20); Fujimoto, Ho, and Sonego (for claim 21); and adding Ohkawa (Patent 6,091,154) to the primary combinations to teach a self-aligned contact step (for claims 15 and 23). These grounds relied on similar arguments of combining known process steps from the prior art to achieve predictable results.

4. Relief Requested

  • Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 1-23 of Patent 6,559,044 as unpatentable.