PTAB

IPR2017-01431

STMicroelectronics Inc v. Semcon IP Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Adaptive Power Control
  • Brief Description: The ’627 patent describes a system and method for controlling power consumption in a computer system. The invention focuses on dynamic voltage and frequency scaling, where a processor monitors its own operating conditions and adjusts its clock frequency and supply voltage to optimize power usage based on processing demands.

3. Grounds for Unpatentability

Ground 1: Anticipation over Yamamoto - Claims 1-5, 9-12, 16-20, and 23-25 are anticipated by Yamamoto.

  • Prior Art Relied Upon: Yamamoto (Patent 5,778,237).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Yamamoto discloses every limitation of the challenged claims. Yamamoto teaches a microcomputer that reduces power by changing the frequency and voltage of various circuit modules, including a central processing unit and other components (e.g., memory, timers). It discloses a programmable clock generator (the claimed "frequency generator") that receives an input clock signal and generates multiple, individually adjustable output clock signals for the processing unit and a "second component." Crucially, Petitioner asserted that Yamamoto discloses the key limitation added during prosecution: initiating a frequency change triggers a timer (the claimed "counter"), shuts down the clocks, and then turns the clocks back on after the timer reaches a predetermined value to allow for stabilization.
    • Key Aspects: The core of this ground rested on mapping Yamamoto's "timer" and clock gating process to the ’627 patent's "counter" and clock shutdown/restart sequence, which was the feature that overcame examiner rejections during prosecution.

Ground 2: Obviousness over Yamamoto in view of Jackson - Claims 4, 7, 12, 14, 18, 19, and 22 are obvious over Yamamoto in view of Jackson.

  • Prior Art Relied Upon: Yamamoto (Patent 5,778,237) and Jackson (Patent 5,825,674).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground addressed claims requiring frequency and voltage adjustments to be "responsive to a change in operating conditions," such as temperature. Petitioner argued that Yamamoto discloses adjusting frequency based on the operating condition of task demand (high-speed vs. low-speed processing). Jackson discloses a system for controlling power consumption in a mobile device that explicitly monitors processor temperature with a thermal sensor and reduces frequency and voltage when the temperature exceeds a thermal band. The combination of Yamamoto's architecture with Jackson's temperature monitoring function renders the claims obvious.
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would have been motivated to combine the teachings because both Yamamoto and Jackson address the same problem of dynamic power management in computer systems. A POSITA would combine Jackson’s well-known technique of temperature monitoring with Yamamoto's dynamic power control system to provide an additional, useful condition for adjusting performance. This would have been a predictable combination of known elements to improve the system's robustness.
    • Expectation of Success: A POSITA would have had a reasonable expectation of success in implementing this combination. Integrating a known thermal sensor and control logic (from Jackson) into a microcomputer with dynamic frequency control (from Yamamoto) was a straightforward application of known design principles to yield a predictable result.

Ground 3: Obviousness over Yamamoto in view of Harper - Claim 26 is obvious over Yamamoto in view of Harper.

  • Prior Art Relied Upon: Yamamoto (Patent 5,778,237) and Harper (Patent 5,560,024).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground targeted claim 26, which adds a "means for maintaining time consistency between a clock for said processing unit and real world time after adjusting clock frequency." Petitioner contended that while Yamamoto teaches adjusting the processor clock frequency, it does not explicitly disclose maintaining consistency with real-world time. Harper, which relates to low-power management for portable computers, discloses a "time update" mode to maintain the time-of-day across various operating modes.
    • Motivation to Combine: A POSITA would combine Harper’s time-keeping functionality with Yamamoto's power-saving system to ensure that system time remains accurate, a common and desirable feature. As computer systems change clock speeds for power management, ensuring the real-time clock is not adversely affected is a logical and necessary design consideration.
    • Expectation of Success: Integrating a time-of-day clock and associated update logic into a microcomputer was a well-understood task at the time, leading to a high expectation of success.

4. Key Claim Construction Positions

  • "processing unit": Petitioner proposed the construction "computing portion of the processor." This construction was used to distinguish the core computational logic from other on-chip components like the frequency generator, aligning with the patent's description and allowing for a clear mapping of claim elements to the prior art.
  • "second component": Petitioner proposed the construction "component of the computer system separate from the processing unit." This broad construction was important for the invalidity arguments, as it allowed components in Yamamoto such as system memory, a direct memory access controller (DMAC), or timers to satisfy the "second component" limitation.

5. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1-5, 7, 9-12, 14, 16-20, and 22-26 of the ’627 patent as unpatentable.