STMicroelectronics Inc v. Semcon IP Inc

1. Case Identification

• Case #: IPR2017-01432
• Patent #: 5,978,876
• Filed: May 12, 2017
• Petitioner(s): STMicroelectronics, Inc.
• Patent Owner(s): Semcon IP, Inc.
• Challenged Claims: 1-19

2. Patent Overview

• Title: System and Method for Controlling Communications Between Subsystems
• Brief Description: The ’876 patent discloses a system for providing dynamic and centralized control of communications between subsystems connected over a shared data bus. A communications coordinator assigns specific "time-based transfer-window channels" to pairs of subsystems to enable direct data exchange without requiring conventional subsystem addressing for the data transfer itself.

3. Grounds for Unpatentability

Ground 1: Anticipation - Claims 1-17 are anticipated by Lambrecht

• Prior Art Relied Upon: Lambrecht (Patent 5,682,484) and Intel DMAC (The Intel Peripherals Handbook, 1994 Edition), which is expressly incorporated by reference into Lambrecht.
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Lambrecht, alone or in combination with the incorporated Intel DMAC datasheet, disclosed every limitation of claims 1-17. Lambrecht’s system for transferring real-time data between multimedia devices teaches a central controller (CPU or I/O processor) that functions as the claimed "communications coordinator." This controller dynamically assigns time-sliced communication windows ("time slots") on a multimedia bus, which Petitioner contended are the same as the ’876 patent's "communications channels." Lambrecht’s multimedia devices are connected in parallel and communicate directly during their assigned time slots, meeting the claim limitations for direct communication between subsystems. For dependent claims requiring specific coordinator components, Petitioner mapped Lambrecht’s I/O processor and its data bus registers to the claimed "first processor" and "first processor memory." The incorporated Intel DMAC reference was cited to explicitly teach a "message length counter" (word count register) that is decremented with each transfer, satisfying limitations in claims 6 and 17.
  • Key Aspects: The core of this ground was the direct mapping of Lambrecht’s time-slot allocation system for multimedia devices to the ’876 patent's channel-based communication control system.

Ground 2: Obviousness over Lambrecht and General Skill - Claims 3-19 are obvious over Lambrecht in view of the knowledge of one of skill in the art

• Prior Art Relied Upon: Lambrecht (Patent 5,682,484) and the general knowledge of a Person of Ordinary Skill in the Art (POSITA).
• Core Argument for this Ground:
  • Prior Art Mapping: As an alternative to anticipation, Petitioner argued that to the extent any feature of the dependent claims was not expressly disclosed in Lambrecht, it would have been an obvious modification. For example, features such as using video cards as subsystems (claim 3), implementing a message length counter (claim 6), or monitoring bus communications to evaluate and implement the "most appropriate" channel (claims 11-12) were all well-known, fundamental concepts in computer architecture and DMA controller design at the time. Petitioner noted that during the original prosecution, the Examiner took "Official Notice" that many of these dependent claim features were well-known, an assertion the applicant did not rebut.
  • Motivation to Combine (for §103 grounds): A POSITA designing a system like Lambrecht’s, with the goal of optimizing real-time data transfer, would have been motivated to incorporate these well-known features to improve system reliability, control, and performance. Using standard components like message counters was a predictable way to manage data transfers.
  • Expectation of Success (for §103 grounds): A POSITA would have had a high expectation of success in implementing these conventional features into Lambrecht's system, as they represented standard design choices for bus controllers.

Ground 3: Obviousness over Lambrecht and Craft - Claims 16, 18, and 19 are obvious over Lambrecht in view of Craft

• Prior Art Relied Upon: Lambrecht (Patent 5,682,484) and Craft (Patent 5,438,666).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground specifically addressed claims requiring "dynamically and interruptably reassigning" a channel (claim 16) and "pausing" communications for higher-priority transfers (claims 18-19). Petitioner argued that while Lambrecht taught a base system for dynamically assigning communication channels, Craft taught a bus arbitration system that explicitly addresses interrupting ongoing communications. Craft disclosed pausing a communication cycle on a shared bus to grant control to a device with a higher-priority request, and then returning control to the original device to complete its transfer.
  • Motivation to Combine (for §103 grounds): A POSITA would combine Craft’s known bus arbitration and interrupt technique with Lambrecht’s system to enhance data transfer performance and make the system more responsive to real-time requirements, a stated goal of the Lambrecht invention. Adding an interrupt mechanism was a known way to handle time-critical operations (like DMA transfers) on a shared bus without compromising system integrity.
  • Expectation of Success (for §103 grounds): A POSITA would have reasonably expected success in combining these systems because both references addressed the common problem of optimizing data transfer on a shared communications bus and used compatible, well-understood principles of computer architecture.

4. Key Claim Construction Positions

• "channel": Petitioner argued this term should be construed to mean a "time-based transfer-window." This construction was based on the ’876 patent’s specification, which repeatedly and explicitly equated the term "communications channel" with a "time-based transfer-window channel designation." This construction was critical to mapping Lambrecht's "time slots" directly onto the claimed "channels."
• "allocation queue": Petitioner proposed this term means "storage for assigned and available channel codes." This construction supported mapping the claim element onto the data bus registers or memory within Lambrecht’s I/O processor, which stored information about time slot assignments. It also addressed the alternative interpretation of a priority arbitration queue by pointing to arbitration logic in Lambrecht and priority schemes in the incorporated Intel DMAC reference.

5. Relief Requested

• Petitioner requested the institution of an inter partes review and the cancellation of claims 1-19 of the ’876 patent as unpatentable.