PTAB

IPR2017-01560

Micron Technology, Inc. v. Lone Star Silicon Innovations, LLC

Title: Method of Forming a Contact Hole in an Interlevel Dielectric Layer Using Dual Etch Stops
Brief Description: The ’188 patent describes a method for fabricating semiconductor devices, specifically for forming a contact hole through an interlevel dielectric (ILD) layer to connect to a transistor's source/drain region. The method uses a three-layer ILD and a three-step sequential etching process with dual etch stops to prevent damaging the underlying silicon substrate, a problem allegedly associated with prior art methods.

Prior Art Relied Upon: Hashimoto (Japanese Patent Publication No. JP H9-64297).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Hashimoto teaches every limitation of the challenged claims. Like the ’188 patent, Hashimoto addresses the problem of preventing damage to the diffusion layer (source/drain region) during contact hole etching. It discloses a method for manufacturing a DRAM device that includes forming a three-layer interlevel dielectric (silicon oxide / silicon nitride / silicon oxide) over a source/drain region. Hashimoto then explicitly teaches a three-step anisotropic, highly selective etch process to form a contact hole, using the intermediate silicon nitride and silicon oxide layers as sequential etch stops, which Petitioner contended is the same fundamental process claimed in the ’188 patent.
- Motivation to Combine (for §103 grounds): Not applicable as this is a single-reference ground.
- Expectation of Success (for §103 grounds): Not applicable.

Prior Art Relied Upon: Hashimoto (JP H9-64297) and Sung (Patent 5,550,078).
Core Argument for this Ground:
- Prior Art Mapping: This ground targets claim 20, which adds the step of forming a "metal-1 pattern" on the first dielectric layer that contacts the conductive plug. Petitioner asserted that Hashimoto’s process for creating a DRAM memory cell inherently requires this step to be functional. Sung was cited as explicitly teaching the conventional process of forming a metal-1 layer (e.g., aluminum copper) over a first interlevel dielectric to interconnect conductive plugs after they are formed in contact holes.
- Motivation to Combine (for §103 grounds): A person of ordinary skill in the art (POSITA) would combine the teachings because both references are in the same field of DRAM fabrication and address creating device interconnects. A POSITA implementing Hashimoto’s process would be motivated to look to a conventional method, like that taught by Sung, to complete the device by forming the necessary metal-1 interconnect layer, a standard and required step for a functional DRAM.
- Expectation of Success (for §103 grounds): A POSITA would have a high expectation of success, as forming a metal-1 layer was a standard, well-known procedure in DRAM manufacturing at the time.

Prior Art Relied Upon: Hashimoto (JP H9-64297) and Kawai (Japanese Patent Publication No. JPH8-46173).
Core Argument for this Ground:
- Prior Art Mapping: This ground challenges claims requiring the first and third dielectric layers to be the same material (e.g., claim 21). Hashimoto discloses using different oxide-based materials (BPSG and NSG) for these layers. Petitioner argued Kawai, which also discloses a three-layer oxide-nitride-oxide structure for DRAM fabrication, explicitly teaches using the same material (TEOS, a type of silicon dioxide) for both the first and third dielectric layers.
- Motivation to Combine (for §103 grounds): A POSITA would be motivated to modify Hashimoto’s process with Kawai’s teaching to simplify manufacturing. Using the same material for the outer dielectric layers, as taught by Kawai, allows for the use of the same etch conditions for multiple steps, reducing complexity, cost, and the likelihood of errors compared to Hashimoto's method which required different etch parameters for its different oxide layers.
- Expectation of Success (for §103 grounds): Success would be expected because it represents a simple design choice to streamline a known manufacturing process, and Kawai demonstrates the viability of this approach.

Prior Art Relied Upon: Hashimoto (JP H9-64297), Kawai (JPH8-46173), and Sung (’078 patent).
Core Argument for this Ground:
- Prior Art Mapping: This ground adds the limitation of planarizing the interlevel dielectric via chemical-mechanical polishing (CMP) before forming the photoresist layer (claim 28). While Hashimoto’s figures show an uneven topology, the reference is silent on planarization. Petitioner contended that Sung explicitly teaches using CMP to planarize an interlevel dielectric layer in a DRAM process to create a smooth topology necessary for subsequent high-resolution photolithography.
- Motivation to Combine (for §103 grounds): A POSITA implementing the process of Hashimoto and Kawai would recognize the need for planarization to ensure the reliability of subsequent patterning steps. They would be motivated to incorporate the well-known CMP technique taught by Sung to solve this known problem, thereby improving the overall manufacturing process.
- Expectation of Success (for §103 grounds): A POSITA would have a high expectation of success, as Sung directs its CMP teaching to the same type of silicon-oxide based dielectric layer created in the Hashimoto/Kawai combined process.

Petitioner proposed a construction for the term “source/drain contact” as “a contact area used to electrically couple a conductive member (for example, a conductive plug) to the source/drain region.” Petitioner argued this construction is supported by the specification and that the "source/drain contact" is not necessarily a separate structure but can be the top of the source/drain region itself. This interpretation is important because it allows prior art that etches down to the source/drain region directly to meet the claim limitation.

Petitioner requests the institution of an inter partes review and the cancellation of claims 1-5, 7-13, 15-23, and 25-29 of the ’188 patent as unpatentable under 35 U.S.C. §103.