PTAB

IPR2017-01560

Micron Technology Inc v. Lone Star Silicon Innovations LLC

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Method of Forming a Contact Hole in an Interlevel Dielectric Layer Using Dual Etch Stops
  • Brief Description: The ’188 patent discloses a semiconductor fabrication method for creating contact holes through an interlevel dielectric (ILD) layer. The method uses a three-layer ILD and a sequence of three distinct, highly selective etches, where the second and third dielectric layers serve as dual etch stops to prevent damage to the underlying source/drain regions.

3. Grounds for Unpatentability

Ground 1: Obviousness over Hashimoto - Claims 1-5, 8-13, 15, and 18-19 are obvious over Hashimoto.

  • Prior Art Relied Upon: Hashimoto (Japanese Patent Publication No. JP H9-64297).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Hashimoto teaches all limitations of the challenged claims. Hashimoto addresses the same problem of preventing substrate damage during contact hole etching in DRAM manufacturing. It discloses a method using a three-layer ILD (silicon oxide, silicon nitride, silicon oxide) and a corresponding three-step anisotropic, highly selective etch process. The process uses the intermediate silicon nitride layer and the bottom silicon oxide layer as sequential etch stops, mirroring the core inventive concept of the ’188 patent.
    • Motivation to Combine (for §103 grounds): This ground is based on a single reference. Petitioner asserted that Hashimoto alone renders the claims obvious, but to the extent any minor modifications are needed, a person of ordinary skill in the art (POSA) would have been motivated to implement them based on general knowledge to optimize a known process. For example, a POSA would have understood that Hashimoto's "interlayer insulation film" is an "interlevel dielectric layer" in the context of DRAM manufacturing.
    • Expectation of Success (for §103 grounds): A POSA would have a high expectation of success as Hashimoto provides a detailed, enabling disclosure of the specific etching chemistries, process parameters, and resulting structures.

Ground 2: Obviousness over Hashimoto in view of Sung - Claim 20 is obvious over Hashimoto in view of Sung.

  • Prior Art Relied Upon: Hashimoto (JP H9-64297) and Sung (Patent 5,550,078).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground targets claim 20, which adds the step of "forming a metal-1 pattern on the first dielectric layer that contacts the conductive plug." Petitioner argued that while Hashimoto teaches forming a DRAM device that would inherently require metallization to be functional, Sung explicitly discloses this claimed step. Sung teaches forming a metal-1 layer over an ILD to connect conductive plugs as a standard part of completing a DRAM device.
    • Motivation to Combine (for §103 grounds): A POSA would combine Hashimoto and Sung because both address DRAM fabrication and seek to solve problems related to creating reliable, fine-pattern contacts. A POSA implementing Hashimoto's method would have been motivated to look to conventional techniques, such as those taught by Sung, to complete the device by adding the necessary metal interconnect layer, which Hashimoto implies but does not detail.
    • Expectation of Success (for §103 grounds): Success was expected because adding a metal-1 layer was a standard, well-understood final step in the DRAM manufacturing process at the time, and Sung provides a conventional method for doing so.

Ground 3: Obviousness over Hashimoto in view of Kawai - Claims 7, 16-17, 21-23, and 25-27 are obvious over Hashimoto in view of Kawai.

  • Prior Art Relied Upon: Hashimoto (JP H9-64297) and Kawai (JP H8-46173).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground targets claims requiring the first and third dielectric layers to be made of the "same material." Hashimoto discloses using different materials (BPSG for the first layer, NSG for the third). Petitioner asserted that Kawai remedies this by explicitly teaching an ILD structure where the first and third layers are the same material (TEOS silicon oxide).
    • Motivation to Combine (for §103 grounds): A POSA would combine the references to simplify the manufacturing process taught by Hashimoto. Using the same material for the first and third dielectric layers, as taught by Kawai, would reduce the number of deposition and etch steps, simplifying the process and reducing the likelihood of errors. This is a simple design choice aimed at improving manufacturing efficiency.
    • Expectation of Success (for §103 grounds): A POSA would have a reasonable expectation of success because Kawai teaches that its process works effectively, and substituting one type of silicon oxide for another in the Hashimoto process would be a straightforward modification for a skilled artisan.
  • Additional Grounds: Petitioner asserted an additional obviousness challenge (Ground 4) against claims 28 and 29 based on the combination of Hashimoto, Kawai, and Sung, incorporating the teachings of planarizing the dielectric layer (from Sung) into the simplified process (from Kawai).

4. Key Claim Construction Positions

  • "source/drain contact": Petitioner proposed that this term should be construed as "a contact area used to electrically couple a conductive member (for example, a conductive plug) to the source/drain region." Critically, Petitioner argued that based on the patent's specification and dependent claims, the "source/drain contact" is not necessarily a separate structure but can be the top surface of the source/drain region itself. This construction is central to arguing that prior art references, which show etching down to the source/drain region, meet this limitation.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-5, 7-13, 15-23, and 25-29 of the ’188 patent as unpatentable.