PTAB

IPR2017-01561

Micron Technology Inc v. Lone Star Silicon Innovations LLC

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Method of Forming a Contact Hole in an Interlevel Dielectric Layer Using Dual Etch Stops
  • Brief Description: The ’188 patent discloses a semiconductor fabrication method for creating a contact hole through a three-layer interlevel dielectric (ILD). The method uses the second and third dielectric layers as two distinct, sequential etch stops to improve process control and prevent damaging the underlying source/drain region during etching.

3. Grounds for Unpatentability

Ground 1: Obviousness over Kawai - Claims 1-5, 7-13, 15-19, 21-23, and 25-27 are obvious over Kawai.

  • Prior Art Relied Upon: Kawai (Japanese Patent Publication No. JPH8-46173).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Kawai teaches all limitations of the challenged claims. Kawai discloses a method for manufacturing a DRAM device that addresses the same over-etching problems as the ’188 patent. Specifically, Kawai teaches forming a contact hole through a three-layer ILD (comprising a top silicon oxide layer, a middle silicon nitride layer, and a bottom silicon oxide layer) using a sequence of three highly selective etches. In this process, the middle silicon nitride layer serves as the first etch stop for the top oxide etch, and the bottom silicon oxide layer serves as the second etch stop for the middle nitride etch. This process directly maps to the "dual etch stops" method of independent claims 1, 11, and 21. Petitioner asserted that Kawai also discloses the specific materials, relative layer thicknesses, and use of anisotropic etches required by the various dependent claims.
    • Motivation to Combine (for §103 grounds): This ground is primarily based on a single reference. Petitioner asserted that a person of ordinary skill in the art (POSITA) would have understood Kawai’s disclosure of a three-layer dielectric and three-step etch process as a complete method for forming a contact hole. To the extent any claim limitations were not explicitly stated, a POSITA would have been motivated to implement Kawai's method using well-known and conventional semiconductor fabrication techniques to achieve the disclosed result of a precisely formed contact hole in a DRAM device.
    • Expectation of Success: A POSITA would have had a high expectation of success, as Kawai itself describes a functional and advantageous fabrication process. The reference teaches that its method allows contact holes to be "formed stably and with good precision."

Ground 2: Obviousness over Kawai in view of Sung - Claims 20, 28, and 29 are obvious over Kawai in view of Sung.

  • Prior Art Relied Upon: Kawai (Japanese Patent Publication No. JPH8-46173) and Sung (Patent 5,550,078).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground builds upon Kawai's base method to challenge dependent claims related to subsequent processing steps. Petitioner argued that while Kawai teaches the core method of forming the contact hole and a conductive plug (claim 19), Sung supplies the conventional techniques for completing the DRAM structure. Specifically, Sung teaches planarizing the ILD using chemical-mechanical polishing (CMP) prior to forming the photoresist layer (mapping to claim 28). Sung also explicitly teaches forming a metal-1 pattern on the first dielectric layer that contacts the conductive plug to create the necessary interconnects for a functional DRAM device (mapping to claims 20 and 29).
    • Motivation to Combine: A POSITA would combine the teachings of Kawai and Sung because both references are in the same field of DRAM fabrication and address the common goal of creating reliable, self-aligned contacts in high-density devices. A POSITA implementing Kawai's process for forming contact plugs in a DRAM would naturally look to well-known, conventional methods, such as those taught by Sung, to complete the device. Sung's teachings on CMP for planarization and the formation of a metal-1 layer to interconnect the plugs were standard industry practices necessary to build a functional DRAM device, which was the explicit goal of Kawai.
    • Expectation of Success: A POSITA would have had a high expectation of success in combining these references. Applying Sung's standard CMP and metallization processes to the device structure created by Kawai's method was a predictable integration of known technologies. These were routine and necessary steps in DRAM manufacturing, and no technical hurdles would have prevented their successful combination.

4. Key Claim Construction Positions

  • source/drain contact: Petitioner proposed that this term should be construed to mean "a contact area used to electrically couple a conductive member (for example, a conductive plug) to the source/drain region."
  • Importance of Construction: Petitioner argued that under this construction, the "source/drain contact" could be the top surface of the source/drain region itself, rather than a distinct, separate structural layer. This construction was critical to their argument because Kawai discloses etching down to and exposing the source/drain region directly, which then makes contact with the subsequently formed conductive plug.

5. Relief Requested

  • Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 1-5, 7-13, 15-23, and 25-29 of the ’188 patent as unpatentable.