PTAB

IPR2017-01561

Micron Technology, Inc. v. Lone Star Silicon Innovations, LLC

Log In

1. Case Identification

2. Patent Overview

  • Title: Method of Forming a Contact Hole in an Interlevel Dielectric Layer Using Dual Etch Stops
  • Brief Description: The ’188 patent discloses a method for fabricating contact holes in semiconductor devices. The method uses a three-layer interlevel dielectric structure and a sequential three-etch process, where the second and third dielectric layers function as distinct etch stops to prevent damage to the underlying source/drain contact.

3. Grounds for Unpatentability

Ground 1: Obviousness over Kawai - Claims 1-5, 7-13, 15-19, 21-23, and 25-27 are obvious over Kawai in view of the knowledge of a Person of Ordinary Skill in the Art (POSA).

  • Prior Art Relied Upon: Kawai (Japanese Patent Publication No. JPH8-46173).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Kawai discloses all limitations of the challenged claims. Kawai describes a method for manufacturing a DRAM device that involves forming a contact hole through a three-layer interlevel dielectric stack (oxide/nitride/oxide). This process uses a three-step, highly selective etching sequence: (1) a first etch removes the top oxide layer, stopping on the middle nitride layer; (2) a second etch removes the nitride layer, stopping on the bottom oxide layer; and (3) a third etch removes the bottom oxide layer to expose the underlying source/drain region. Petitioner contended this sequence inherently constitutes the claimed "dual etch stop" method.
    • Motivation to Combine (for §103 grounds): This ground relies on Kawai in view of general knowledge. Petitioner asserted that a POSA reading Kawai would be motivated to use the disclosed highly selective etches to achieve the very goal Kawai describes: forming a stable contact opening without damaging underlying layers. For limitations not expressly stated but allegedly inherent (e.g., anisotropic etching), the motivation was to achieve well-known benefits like straight sidewalls, which is consistent with Kawai’s depiction of high-aspect-ratio contacts.
    • Expectation of Success: A POSA would have had a clear expectation of success, as Kawai itself describes a complete and functional process for fabricating semiconductor contacts using the disclosed materials and etching steps.

Ground 2: Obviousness over Kawai and Sung - Claims 20, 28, and 29 are obvious over Kawai in view of Sung.

  • Prior Art Relied Upon: Kawai (Japanese Patent Publication No. JPH8-46173) and Sung (Patent 5,550,078).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground targets dependent claims that add conventional fabrication steps to the base process taught by Kawai. Petitioner argued that Sung, which also relates to DRAM fabrication, explicitly teaches these missing elements. Specifically, Sung teaches forming a metal-1 pattern that contacts a conductive plug (for claim 20) and planarizing an interlevel dielectric layer using chemical-mechanical polishing (CMP) before forming the photoresist layer (for claim 28). Claim 29 combines these and other previously disclosed steps.
    • Motivation to Combine (for §103 grounds): Petitioner argued a POSA would combine Kawai and Sung as both address solving problems in DRAM fabrication. A POSA would have been motivated to complete the DRAM device partially described in Kawai by looking to other contemporaneous art like Sung for standard, well-known finishing steps. Specifically, a POSA would use Sung’s teaching of a metal-1 layer to provide the necessary interconnects for the contact plugs in Kawai’s DRAM cell. Likewise, a POSA would replace Kawai’s cumbersome SOG etch-back planarization with Sung’s more efficient and common CMP process to simplify manufacturing and achieve a smoother surface.
    • Expectation of Success: A POSA would have reasonably expected success in combining these teachings. Applying a metal-1 layer and using CMP were standard, predictable procedures in DRAM manufacturing at the time. The combination involved applying known techniques to a similar device (DRAM) to achieve a predictable result (a functional, interconnected device).

4. Key Claim Construction Positions

  • "source/drain contact": Petitioner argued this term, central to all claims, should be construed as "a contact area used to electrically couple a conductive member (for example, a conductive plug) to the source/drain region." Critically, Petitioner asserted that based on the patent's specification and claims, this "contact" could be the top surface of the source/drain region itself, rather than a separately deposited structure. This construction was vital to Petitioner's argument that Kawai’s disclosure of etching down to expose the source/drain region met this claim limitation.

5. Relief Requested

  • Petitioner requested the institution of an inter partes review and the cancellation of claims 1-5, 7-13, 15-23, and 25-29 of the ’188 patent as unpatentable.