PTAB

IPR2017-01593

LG Electronics Inc v. Broadcom Corp

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: System and Method for Decoding and Displaying Video Frames
  • Brief Description: The ’171 patent discloses a system for displaying digital video at high speed, often called a "trick mode." The system selectively decodes and displays a subset of video frames—including both reference (I- and P-pictures) and non-reference (B-pictures)—while ensuring that the displayed frames are separated by a constant time-lapse to produce smooth playback.

3. Grounds for Unpatentability

Ground 1: Anticipation - Claims 1-8 are anticipated by Jun.

  • Prior Art Relied Upon: Jun (Application # 2002/0039481).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Jun, which discloses an "intelligent fast-forward video system," teaches every limitation of the challenged claims. Jun’s system displays pictures at high speed by selecting frames to realize an "n times play speed." Its "storage part 303" functions as the claimed buffer for storing parameters like play speed and frame intervals. Jun's "skip-player 310" containing a "decode & display" part 311 is the claimed video decoder. The system decodes "particular ones" of the pictures by applying a priority scheme that selects among I-frames, P-frames, and B-frames based on decoding time and desired playback speed. Crucially, Petitioner asserted that Jun’s teaching that frames are "selected to be distributed equally in display time" directly discloses the "constant time-lapse" limitation, which was the basis for allowance during the ’171 patent's prosecution.

Ground 2: Obviousness - Claims 1-8 are obvious over Davenport in view of Hori.

  • Prior Art Relied Upon: Davenport (International Publication No. WO 02/35832) and Hori (Application # 2003/0086692).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner contended that Davenport discloses a video delivery system with a "trick-mode" that meets most claim limitations. Davenport’s system displays a "subset of images" at high speed, including I-frames and optionally P- or B-frames, and provides for "equalized delivery intervals" to create a smooth display, thus teaching the "constant time-lapse." The primary combination addresses the "buffer for storing parameters" limitation. While Davenport discloses an "index file 52" to correlate frames, Petitioner argued Hori supplies the specific parameters that a skilled artisan would have used to implement it.
    • Motivation to Combine: A POSITA would combine Hori’s teachings with Davenport’s system to create a more functional and robust implementation of trick-mode playback. Both references solve the same problem of managing high-speed video display. Davenport discloses the need for an index file to correlate frames for trick-mode transitions, but does not detail its parameters. Hori teaches creating and storing specific "special reproduction control information," including "video location information" and "display time control information," for this exact purpose. A POSITA would have incorporated Hori's detailed parameters into Davenport's index file to achieve the correlations Davenport described.
    • Expectation of Success: A POSITA would have had a high expectation of success, as combining known control data parameters (from Hori) into a system designed to use such data (Davenport) is a predictable design choice.

Ground 3: Obviousness - Claims 1-8 are obvious over Demas in view of Hori.

  • Prior Art Relied Upon: Demas (Application # 2003/0165322) and Hori (Application # 2003/0086692).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Demas discloses a Personal Video Recorder (PVR) system that performs high-speed trick modes (e.g., 2x, 3x, 6x fast-forward) by selectively decoding frames. Demas teaches decoding a subset of frames, including I-, P-, and B-frames, based on host commands. It discloses achieving a "smooth fast forward" by configuring its decoder to display frames for "every vertical synchronization pulse," which Petitioner asserted meets the "constant time-lapse" limitation. As in Ground 2, the combination with Hori primarily addresses the "buffer for storing parameters" limitation.
    • Motivation to Combine: The motivation is analogous to that in Ground 2. Demas discloses using an "index table" with location information from the transport stream to access frames for trick-mode playback. A POSITA would have recognized that Hori's frame-specific "video location information" and "display time control information" would provide more precise control than Demas's potentially less granular index table. To enable the specific frame locating and decoding described by Demas, a POSITA would have integrated Hori's detailed parameters into Demas's indexing system.
    • Expectation of Success: The combination would have been a predictable integration of known techniques to improve the performance of a PVR's trick-mode feature.

4. Key Claim Construction Positions

  • "[a video decoder for] decoding particular ones of the predetermined number of the pictures, wherein the predetermined ones are either reference pictures or pictures that are to be displayed at high speed": Petitioner argued this phrase means the decoder processes some, but not all, of the available pictures, and that the selected pictures include both reference types (I- and P-pictures) and non-reference types (B-pictures). This construction is critical to show that prior art systems which decode I-, P-, and B-frames for trick mode meet the claim limitation.
  • "wherein the pictures that are displayed in high speed at each display interval have a constant time-lapse between the pictures...": Petitioner contended this phrase means the displayed pictures are separated by a constant amount of time, consistent with the patent owner's arguments during prosecution. This construction allows Petitioner to map prior art describing "equal" or "uniform" display intervals (e.g., tied to vertical sync pulses) directly onto this key limitation.

5. Relief Requested

  • Petitioner requests institution of an IPR and cancellation of claims 1-8 of the ’171 patent as unpatentable under 35 U.S.C. §§ 102 and 103.