LG Electronics Inc v. Broadcom Corp

1. Case Identification

• Case #: IPR2017-01624
• Patent #: 8,284,844
• Filed: June 16, 2017
• Petitioner(s): LG Electronics, Inc.
• Patent Owner(s): Broadcom Corporation
• Challenged Claims: 1-14

2. Patent Overview

• Title: Video Decoding System Supporting Multiple Standards
• Brief Description: The ’844 patent relates to a video decoding system that supports multiple video standards by dividing decoding responsibilities between a core processor and a set of configurable hardware accelerators. These accelerators are designed to perform fundamental decoding functions such as variable-length decoding, inverse quantization, inverse transform, and filtering.

3. Grounds for Unpatentability

Ground 1: Anticipation of Claims 1-7, 9-11, and 13 by Diaz

• Prior Art Relied Upon: Diaz (Patent 5,920,353).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Diaz disclosed every element of the challenged claims. Diaz teaches a multi-standard digital media decoding system capable of decoding various formats like MPEG-1, MPEG-2, and H.261. The system uses a processor (processor 75) to control a decoding process performed by multiple hardware modules, which Petitioner asserted are the claimed "hardware accelerators." These accelerators are configurable to perform decoding functions according to a plurality of decoding methods by allowing the processor to dynamically reconfigure the division of labor between software and hardware to accommodate different standards. Petitioner further argued that Diaz disclosed the specific accelerators recited in the dependent claims, including a variable-length code decoder (entropy decoder), an inverse quantizer, an inverse discrete cosine transform (IDCT) circuit, a half-pel filter (pixel filter), and a motion compensation engine.

Ground 2: Obviousness of Claims 8 and 14 over Diaz in view of Purcell

• Prior Art Relied Upon: Diaz (Patent 5,920,353) and Purcell (Patent 5,598,483).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that while Diaz taught the general architecture of a processor controlling configurable hardware accelerators, it did not explicitly disclose the specific control mechanism recited in claims 8 and 14. Claim 8 requires that the accelerator include registers that are programmed by the main processor to configure the accelerator. Claim 14 adds that the processor reads these registers to derive operational status. Petitioner argued that Purcell taught this exact implementation. Purcell disclosed an MPEG decompression processor that controlled multiple hardware "coprocessors" (accelerators) by writing to and reading from globally addressable control and data registers associated with each coprocessor. These registers dictate operational parameters and allow the main processor to monitor status.
  • Motivation to Combine: A POSITA would combine Diaz's flexible multi-standard architecture with Purcell's known and efficient coprocessor control-register implementation. Diaz described a high-level system for multi-standard decoding, and Purcell provided a well-understood, economical, and real-time hardware implementation for controlling such decoding blocks. A POSITA would have looked to a reference like Purcell to implement the control functionality generally described in Diaz.
  • Expectation of Success: The combination would have yielded predictable results. Implementing the hardware accelerators of Diaz using the control register and internal processor architecture from Purcell would predictably achieve an efficient, real-time decoding system, as the elements would perform their known functions in the combined system.

Ground 3: Obviousness of Claim 12 over Diaz in view of Fandrianto

• Prior Art Relied Upon: Diaz (Patent 5,920,353) and Fandrianto (Patent 5,982,459).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner argued that Diaz anticipated parent claim 11 by disclosing a plurality of hardware accelerators, but did not explicitly disclose that one of these accelerators was a "de-blocking filter" as recited in claim 12. Fandrianto, however, explicitly taught this feature. Fandrianto disclosed a multimedia processor containing a hardware accelerator (video processor 280) that performs post-decompression processing, including applying a de-blocking or smoothing filter to decoded frames to improve picture quality by reducing blocking artifacts.
  • Motivation to Combine: A POSITA would be motivated to add the de-blocking filter taught by Fandrianto to the multi-accelerator system of Diaz. Fandrianto provided the explicit motivation: to "reduce blocking artifacts often visible at low bit rates," a well-known problem in the field of video compression. Since both Diaz and Fandrianto address multi-standard video decoding, a POSITA seeking to improve the output quality of the Diaz system would have incorporated a de-blocking filter.
  • Expectation of Success: Adding a de-blocking filter was a well-known technique for improving visual quality in the art. Incorporating Fandrianto's de-blocking filter into Diaz's system would have been a straightforward application of a known element to yield the predictable result of improved picture quality.

• Additional Grounds: Petitioner asserted an additional obviousness challenge against claim 12 over Diaz in view of Kim (a 1999 journal article), which also taught a de-blocking filter to improve visual quality in low bit-rate video coding. This ground relied on a similar design modification theory as the challenge based on Fandrianto.

4. Relief Requested

• Petitioner requested institution of an inter partes review and cancellation of claims 1-14 of the ’844 patent as unpatentable under 35 U.S.C. §§ 102 and 103.