PTAB

IPR2017-01670

LG Electronics Inc v. ATI Technologies ULC

Log In
Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: PARALLEL PIPELINE GRAPHICS SYSTEM
  • Brief Description: The ’506 patent discloses a parallel pipeline graphics system built on a single graphics processing chip. The system architecture includes a front-end that receives graphics instructions to generate geometry and a back-end that receives the geometry and processes it for display using two or more parallel pipelines.

3. Grounds for Unpatentability

Ground 1: Obviousness of Claims 1, 8, and 9 over Parsons

  • Prior Art Relied Upon: Parsons (Patent 6,731,288).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Parsons, which was not considered during prosecution, taught all key limitations of independent claim 1. Parsons disclosed a 3D graphics processing unit (a "graphics chip") with a "Transform and Lighting Subsystem" that served as the claimed front-end, configured to receive instructions and output geometry. Petitioner contended that Parsons’ back-end, which included a Texture Subsystem with multiple parallel "Texture Pipes," directly mapped to the claimed "back-end in the graphics chip comprises multiple parallel pipelines." For dependent claims, Petitioner asserted that Parsons' programmable Texture Pipes, which could perform both color and texture operations, met the "unified shader" limitation of claim 9. Furthermore, Parsons' disclosure of multi-pass operations and anisotropic filtering loops was argued to teach the "loop back" functionality required by claim 8.
    • Motivation to Combine: Not applicable for a single-reference ground.
    • Expectation of Success: Not applicable for a single-reference ground.

Ground 2: Obviousness of Claims 1, 6, 8, and 9 over Parsons in view of Donham and Gibson

  • Prior Art Relied Upon: Parsons (Patent 6,731,288), Donham (Patent 6,980,209), and Gibson (Patent 6,750,867).
  • Core Argument for this Ground:
    • Prior Art Mapping: This combination was presented to provide more explicit teachings for claim 1 and to address claim 6. Donham taught a scalable, modular "pixel shader" that could be implemented with any number of identical processing stages, reinforcing the teaching of parallel pipelines with unified shaders. Gibson taught an image processing apparatus with a "tiling device" that divides an image into tiles and allocates them to distinct, parallel rendering devices for processing. Petitioner argued this combination explicitly taught a system where geometry is directed to one of multiple parallel pipelines based on its determined location in a tiled output screen, directly addressing the limitations of claim 6.
    • Motivation to Combine: Petitioner asserted a POSITA would combine these references, all from the same field of graphics processing, to achieve predictable improvements in performance and efficiency. Gibson’s tiling approach was a known method for speeding up rendering in parallel systems, and Donham's scalable architecture was well-suited for such parallel implementation. A POSITA would combine the front-end of Parsons with a back-end based on the parallelized, tiled architecture taught by Donham and Gibson to gain significant efficiency.
    • Expectation of Success: The petition argued that combining modular front-ends and back-ends from different but similar graphics architectures was a common design practice. Therefore, a POSITA would have a reasonable expectation of successfully integrating these known elements.

Ground 3: Obviousness of Claims 2-5 and 7 over Parsons in view of Donham, Gibson, and Zhu

  • Prior Art Relied Upon: Parsons (Patent 6,731,288), Donham (Patent 6,980,209), Gibson (Patent 6,750,867), and Zhu (Patent 6,697,063).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner introduced Zhu to teach the specific internal pipeline components recited in the remaining dependent claims. Zhu disclosed a rendering system that used screen space tiling and a "double-z scheme" to decouple visibility processing from rendering. Zhu’s "scan/z engine" was mapped to the claimed "z-buffer logic unit" (claim 3), "scan converter" (claim 7), and the hierarchical and early Z interfaces (claim 4). Zhu’s blending engine, which could perform z-buffering after shading, was mapped to the late Z interface (claim 5). Zhu also explicitly taught a "large visible fragment FIFO" for load balancing between its scan/z engine and rasterizer, which Petitioner mapped to the FIFO unit of claim 2.
    • Motivation to Combine: A POSITA would be motivated to incorporate Zhu’s teachings into the Parsons/Donham/Gibson system to further increase rendering efficiency. Zhu’s core teaching involved performing visibility culling early, allowing the more computationally expensive rasterizer and shader stages to process only visible primitives, thereby reducing the overall processing load. A POSITA would integrate Zhu’s scan/z engine and FIFO load-balancing unit within each parallel pipeline of the base combination to gain these efficiencies on a per-tile basis.
    • Expectation of Success: A POSITA would reasonably expect to successfully add Zhu's well-understood, efficiency-improving components (scan/z engine, FIFO) into the established parallel pipeline architecture of the primary combination to achieve a more optimized and powerful graphics processor.

4. Key Claim Construction Positions

  • The petition proposed a construction for the term "one or more final pixels" found in claim 1.
  • Petitioner argued that based on the patent's specification and the understanding of a POSITA, the term should be construed to mean pixel(s) that are ready to be passed to a frame buffer for display. This construction was asserted as important for demonstrating how prior art references that output fully processed pixel data to a frame buffer met this limitation.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-9 of the ’506 patent as unpatentable.