PTAB

IPR2017-01671

LG Electronics Inc v. ATI Technologies ULC

Log In
Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: UNIFIED SHADER
  • Brief Description: The ’133 patent relates to a unified shader architecture for computer graphics processing. The disclosed shader is configured with a shading processing mechanism capable of performing both texture operations and color operations using at least one Arithmetic Logic Unit (ALU)/memory pair.

3. Grounds for Unpatentability

Ground 1: Obviousness over Alcorn and Jarvis - Claims 1, 7, and 8 are obvious over Alcorn in view of Jarvis.

  • Prior Art Relied Upon: Alcorn (Patent 5,185,856) and Jarvis (Patent 5,469,535).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Alcorn disclosed the core limitations of independent claim 1, including a unified shader (its pixel cache/ALU) that receives data from a rasterizer and performs both color operations (e.g., blending) and texture operations. Alcorn’s shader was argued to include at least one ALU/memory pair. However, Petitioner noted that Alcorn’s texture data originated from a host processor rather than a dedicated texture unit local to the graphics pipeline. Jarvis was argued to supply this missing element by disclosing an ALU that issues a request to a local texture unit and writes the received texture values back to memory, fulfilling the claimed texture operation limitations.
    • Motivation to Combine: A POSITA would combine the dedicated, local texture unit of Jarvis with Alcorn’s graphics system to reduce latency, increase graphics processing speed, and free up main memory for non-graphics tasks. These were well-known benefits of localizing texture operations within the graphics pipeline instead of relying on the main system CPU and memory.
    • Expectation of Success: Success was expected because implementing a dedicated texture unit was a standard and well-understood modification in graphics pipeline design, representing a predictable solution to a known problem.

Ground 2: Obviousness over Alcorn, Jarvis, and Poulton - Claims 2, 3, and 13 are obvious over Alcorn and Jarvis in view of Poulton.

  • Prior Art Relied Upon: Alcorn (Patent 5,185,856), Jarvis (Patent 5,469,535), and Poulton (Patent 5,481,669).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon the combination in Ground 1. Petitioner argued that Poulton supplied the limitations of claims 2 and 3 by teaching the use of a valid-ready protocol to synchronize data transfers. Poulton disclosed a ready/go controller with ready and go chains to manage pixel data transfers between system components, including from a rasterizer to a shader and from the shader to a frame buffer. For claim 13, Poulton was argued to teach the recited functional capabilities of an ALU/memory pair, including writing texture addresses and color values to memory, reading source operands, and executing shader instructions.
    • Motivation to Combine: A POSITA would incorporate Poulton's synchronization protocol into the Alcorn/Jarvis system to ensure precise and efficient data transfer. Such synchronization was a known necessity for managing data flow in complex, pipelined graphics architectures to prevent data loss or corruption.
    • Expectation of Success: Success was expected because all three references relate to shaded image generation techniques and share similar structures, objectives, and operations, making their combination straightforward for a POSITA.

Ground 4: Obviousness over Alcorn, Jarvis, and Rich - Claims 9 and 10 are obvious over Alcorn and Jarvis in view of Rich.

  • Prior Art Relied Upon: Alcorn (Patent 5,185,856), Jarvis (Patent 5,469,535), and Rich (Patent 5,923,338).

  • Core Argument for this Ground:

    • Prior Art Mapping: Building upon Ground 1, Petitioner argued that Rich taught the limitations of claim 9: a plurality of ALU/memory pairs that constitute a single coherent memory structure and are synchronized by a scheduling clock mechanism. Rich disclosed an array of processing elements, each containing an ALU and its own dedicated memory bank, which Petitioner asserted constituted a single, coherent structure rather than disparate caches. Rich also taught that these elements operate simultaneously, instructed by a control unit using clock cycles, thus providing the claimed scheduling clock mechanism.
    • Motivation to Combine: A POSITA would combine the discrete memories of Alcorn/Jarvis into a single coherent structure as taught by Rich to reduce hardware costs and simplify the overall system design. Further, synchronizing the ALU/memory pairs was a known method to reduce the inefficiencies associated with processing graphics primitives piecemeal over multiple clock cycles.
    • Expectation of Success: The proposed modification was presented as an obvious engineering choice, as consolidating components and synchronizing parallel processors were common design strategies to improve performance and reduce complexity.

  • Additional Grounds: Petitioner asserted additional obviousness challenges, including: Ground 3 (claims 4-5) using Zatz to teach partitioning code by level of indirection for multipass rendering; Ground 5 (claim 11) using Torii to teach a FIFO memory without an associated buffer; Ground 6 (claim 12) using Storm to teach a FIFO that comprises both data and operation instructions; Ground 7 (claim 6) using Olano, Ashburn, and Hussain to teach control logic with input state, ALU state, and texture machines; and Ground 8 (claim 40) using Rich to teach a plurality of synchronized unified shaders.

4. Key Claim Construction Positions

  • [level of indirection] (Claim 5): Petitioner contended that no formal construction was needed, as the specification defined the term. It was argued to reflect the number of times data passes through the texture system, where each subsequent pass corresponds to a higher level of indirection, a concept relevant for performing complex, multipass rendering techniques.
  • [single coherent memory structure] (Claim 9): Petitioner argued this term should be understood based on its description in the patent’s provisional application. The term was described as replacing multiple conventional FIFOs and buffers with a single structure (e.g., a single FIFO), distinguishing it from architectures with multiple, functionally distinct memory caches (such as separate source, pattern, and destination caches).

5. Relief Requested

  • Petitioner requested the institution of an inter partes review and the cancellation of claims 1-13 and 40 of the ’133 patent as unpatentable.