PTAB

IPR2017-01728

Cavium Inc v. Alacritech Inc

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Petition
petition Intelligence

1. Case Identification

2. Patent Overview

  • Title: Fast-Path Apparatus for Receiving Data Corresponding to a TCP Connection
  • Brief Description: The ’241 patent discloses a system for offloading network protocol processing from a host computer to an intelligent network interface card (INIC). The INIC operates in a "fast-path" mode, where it processes TCP/IP packets independently, or a "slow-path" mode, where packets are passed to the host for conventional processing.

3. Grounds for Unpatentability

Ground 1: Obviousness over Erickson, Tanenbaum96, and Alteon - Claims 1-8, 18, 22, and 23 are obvious over Erickson in view of Tanenbaum96 and Alteon.

  • Prior Art Relied Upon: Erickson (Patent 5,768,618), Tanenbaum96 (A. Tanenbaum, Computer Networks, 3rd ed. (1996)), and Alteon (“Gigabit Ethernet Technical Brief: Achieving End-to-End Performance”).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued Erickson taught an I/O device adapter for fast-path network processing that mentioned TCP but focused on UDP. Tanenbaum96, a widely-cited textbook, supplied the necessary details for TCP fast-path processing, including using header prediction to sort packets into "fast" and "slow" paths. To meet the "without an interrupt dividing" limitation, Petitioner cited Alteon, which taught using a single interrupt for multiple data packets to reduce host CPU load, thereby disclosing header validation without intermediate interrupts. The combination also taught sending packet data directly to application memory without headers, as shown in both Erickson and Alteon.
    • Motivation to Combine: A POSITA would combine Erickson and Tanenbaum96 because Erickson expressly incorporated an earlier edition of the Tanenbaum textbook, directing one of skill in the art to it for TCP details. A POSITA would be further motivated to add Alteon's single-interrupt teaching to the Erickson/Tanenbaum96 system to improve performance and better address the known problem of host processing overhead, which was a central concern of Erickson.
    • Expectation of Success: Petitioner asserted a high expectation of success, as TCP/IP was a well-understood, standardized protocol, and combining these known techniques for protocol offloading and interrupt reduction would yield predictable improvements.

Ground 2: Obviousness over Erickson and Tanenbaum96 - Claims 9-17, 19-21, and 24 are obvious over Erickson in view of Tanenbaum96.

  • Prior Art Relied Upon: Erickson (Patent 5,768,618) and Tanenbaum96 (A. Tanenbaum, Computer Networks, 3rd ed. (1996)).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground focused on transmit-side processing. Petitioner asserted Erickson taught a programmable I/O device (a "second processor") that retrieves data from a host ("first processor"), uses a header template to prepend headers, and transmits the resulting packets. Tanenbaum96 provided the standard TCP-specific steps missing from Erickson's UDP-focused examples, such as dividing data into segments and establishing a TCP connection. The combined teachings disclosed obtaining data, segmenting it, prepending MAC/IP/TCP headers "at one time" using a template on the I/O device, and transmitting the packets.
    • Motivation to Combine: The motivation was the same as in Ground 1: Erickson's explicit reference to Tanenbaum would lead a POSITA to consult it to adapt Erickson's fast-path architecture for the prevalent TCP protocol.
    • Expectation of Success: Success would be expected as it involved applying well-known TCP segmentation and connection management principles to Erickson's established I/O offloading framework.

  • Additional Grounds: Petitioner asserted an additional obviousness challenge (Ground 3) against claims 18, 22, and 23 based on the combination of Erickson, Tanenbaum96, and Alteon, leveraging arguments similar to those presented in Ground 1.

4. Key Claim Construction Positions

  • "[first/second] mechanism": Petitioner argued that "mechanism" is a nonce word lacking sufficient structural definition in the claims, thus invoking means-plus-function treatment under 35 U.S.C. § 112, para. 6. The petition contended that the specification failed to disclose the specific algorithms or corresponding structure necessary to perform the claimed functions (e.g., packet processing, sorting, sending data), rendering claims containing the term indefinite.
  • "without an interrupt dividing": Petitioner argued this phrase is indefinite. They contended a POSA would not understand how a host processor interrupt could "divide" header validation processing that, in the context of the patent's "fast-path," occurs on the separate INIC, not the host processor.

5. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1-24 of the ’241 patent as unpatentable.