PTAB

IPR2017-01729

Cavium Inc v. Alacritech Inc

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1. Case Identification

2. Patent Overview

  • Title: Intelligent Network Interface System and Method for Protocol Processing
  • Brief Description: The ’948 patent describes a system for offloading Transmission Control Protocol (TCP) processing from a host computer to an intelligent network interface card (INIC). The INIC uses a "fast path" to bypass the host's protocol stack for normal data packets and a "slow path" to direct packets with certain exception conditions to the host for conventional processing.

3. Grounds for Unpatentability

Ground 1: Obviousness over Thia, Tanenbaum96, and Stevens2 - Claims 1, 3, 6-9, 11, 14-17, 19, 21-22 are obvious over Thia in view of Tanenbaum96 and Stevens2.

  • Prior Art Relied Upon: Thia (a 1995 article on a Reduced Operation Protocol Engine), Tanenbaum96 (a 1996 textbook on Computer Networks), and Stevens2 (a 1995 textbook on TCP/IP Implementation).
  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued that Thia teaches a hardware-based protocol offload engine for a generic, multi-layer protocol (OSI) that uses a "fast path" and "slow path" architecture. Thia's engine performs a "receive bypass test" on a network interface to determine if an incoming packet is "normal" and can bypass the host's standard protocol stack (SPS). Packets failing the test are processed by the host's SPS. Petitioner contended that adapting Thia's general architecture to the dominant TCP/IP protocol was obvious. For implementation details, a person of ordinary skill in the art (POSITA) would have consulted standard, authoritative textbooks like Tanenbaum96 and Stevens2.

    • Both Tanenbaum96 and Stevens2 taught the well-known "Header Prediction" algorithm for TCP/IP, which provides the exact "exception conditions" for a bypass test as claimed in the ’948 patent. This algorithm checks if a packet belongs to an ESTABLISHED connection, is in-sequence, is not fragmented, and lacks control flags (e.g., SYN, FIN, RST). Packets meeting these criteria are "normal" and processed on a fast path, while others (exception packets) are handled by the main protocol stack. The combination of Thia's hardware architecture with the specific TCP/IP fast-pathing rules from Tanenbaum96 and Stevens2 allegedly rendered the challenged claims obvious. Thia further taught using Direct Memory Access (DMA) to transfer the payload data of bypassed packets directly to host memory, eliminating headers and avoiding unnecessary data copying, as claimed.

    • Motivation to Combine: A POSITA would combine these references to improve network performance, a central goal in the field. Thia explicitly stated its bypass concept could be used with "any standard protocol," and by 1996, TCP/IP was the dominant standard, making it an obvious choice for implementation. A POSITA seeking to apply Thia's offload architecture to TCP/IP would naturally turn to widely-used textbooks like Tanenbaum96 and Stevens2, which described the standard method for fast-pathing TCP/IP: Header Prediction. Thia's "receive bypass test" was described as a generalization of Jacobson's Header Prediction, the very algorithm detailed in Tanenbaum96 and Stevens2, creating a direct technical link between the references. The motivation was to reduce the processing burden on the host CPU by offloading the handling of common, normal data packets to dedicated hardware.

    • Expectation of Success: A POSITA would have had a reasonable expectation of success. Header Prediction was a well-understood, widely implemented, and thoroughly documented algorithm for TCP/IP processing. Integrating this known software algorithm into a hardware offload architecture like that described in Thia would have been a straightforward engineering task using predictable and conventional techniques.

4. Relief Requested

  • Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 1, 3, 6-9, 11, 14-17, 19, 21-22 of the ’948 patent as unpatentable.