PTAB

IPR2017-01733

Cavium Inc v. Alacritech Inc

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Fast-Path Apparatus for Receiving Data Corresponding to a TCP Connection
  • Brief Description: The ’241 patent relates to a system for offloading Transmission Control Protocol (TCP) processing from a host computer to an intelligent network interface card (INIC). The INIC is designed to provide a "fast-path" that avoids the host's protocol stack for established TCP connections, thereby reducing host CPU utilization and improving network performance.

3. Grounds for Unpatentability

Ground 1: Claims 9-15, 17, and 19-21 are obvious over Connery in view of the knowledge of a POSA.

  • Prior Art Relied Upon: Connery (Patent 5,937,169).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Connery, which teaches offloading TCP segmentation to a "smart adapter," discloses or renders obvious every limitation of the challenged claims. Connery describes a system where a host processor (a "first processor") provides a large data payload and a header template to the smart adapter. A processor on the adapter (a "second processor") then segments the data and creates packet headers—including Media Access Control (MAC), Internet Protocol (IP), and TCP layers—from the provided template before transmission.
    • For claim 9, Petitioner mapped Connery's host CPU and memory to the "first processor" and its memory, and Connery's smart adapter CPU to the "second processor." Petitioner contended Connery's disclosure of segmenting a large datagram on the adapter meets the "dividing the data" limitation. While Connery does not explicitly state headers are "prepended," Petitioner argued a person of ordinary skill in the art (POSA) would find it obvious to prepend headers to data segments for efficiency, rather than performing a more resource-intensive append operation. Similarly, a POSA would find it obvious to perform the header creation, based on Connery's contiguous template header, "at one time as a sequence of bits."
    • For claim 17, which is substantially similar to claim 9, Petitioner relied on the same mappings. Regarding the limitation "without an interrupt dividing the prepending," Petitioner argued this was obvious from Connery's stated goal of reducing host interrupts. Connery teaches reducing interrupts to one per large datagram, so a POSA would understand that the rapid, sequential prepending of headers for the resulting smaller packets on the smart adapter would not involve or be divided by individual host interrupts.
    • Motivation to Combine (for §103 grounds): The primary motivation cited was to implement the protocol offloading system of Connery using well-known and efficient engineering practices. A POSA would be motivated to prepend headers and perform this as a single atomic operation on the network card to achieve Connery's own stated goals of reducing host CPU utilization and improving performance.
    • Expectation of Success (for §103 grounds): A POSA would have had a high expectation of success because the proposed modifications involved applying conventional and predictable networking hardware and software design principles to Connery's architecture.
    • Key Aspects: The viability of this entire ground rested on Petitioner's argument that Connery qualifies as prior art, which required invalidating the ’241 patent's claim to an earlier priority date.

4. Key Claim Construction Positions

  • "[first/second] mechanism" (claim 17): Petitioner argued this term should be construed under 35 U.S.C. §112, paragraph 6 (pre-AIA) as a means-plus-function limitation. Petitioner contended that "mechanism" is a nonce word and that the specification fails to disclose the necessary corresponding structure, such as a specific algorithm, required to perform the claimed functions (e.g., "providing a block of data," "dividing the block of data"). Therefore, Petitioner asserted the term is indefinite.
  • "without an interrupt dividing" (claim 17): Petitioner argued this phrase is indefinite. The contention was that a POSA would not understand how a host processor interrupt could "divide" a header prepending process that occurs entirely on a separate processor located on the network interface card, as the host is not involved in that specific operation.

5. Key Technical Contentions (Beyond Claim Construction)

  • Priority Date Challenge: A central contention of the petition was that the ’241 patent was not entitled to its claimed priority date of October 14, 1997. Petitioner argued that the 1997 provisional application lacked adequate written description support for key limitations recited in the challenged independent claims, including "prepending a packet header" and prepending headers "at one time as a sequence of bits." By successfully challenging the priority date, Petitioner sought to establish Connery, which was filed on October 29, 1997, as valid prior art against all challenged claims.

6. Relief Requested

  • Petitioner requested the institution of an inter partes review (IPR) and the cancellation of claims 9-15, 17, and 19-21 of the ’241 patent as unpatentable.