RPX Corp v. Iym Technologies LLC

1. Case Identification

• Case #: TBD
• Patent #: 7,448,012
• Filed: July 28, 2017
• Petitioner(s): RPX Corporation and Advanced Micro Devices, Inc.
• Patent Owner(s): IYM Technologies LLC
• Challenged Claims: 1-11, 13-14

2. Patent Overview

• Title: Generating Design Layout Artwork
• Brief Description: The ’012 patent describes a computer-implemented method for improving integrated circuit (IC) yield and performance. The method modifies design rule constraints, which are typically global in nature, by applying local process modifications to account for specific local conditions within an IC layout.

3. Grounds for Unpatentability

Ground 1: Obviousness over Allan - Claims 1-5, 10-11, and 13-14 are obvious over Allan.

• Prior Art Relied Upon: Allan (a 1992 IEEE journal article titled “An Yield Improvement Technique for IC Layout Using Local Design Rules”).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Allan, published over a decade before the ’012 patent, discloses all limitations of the challenged claims. Allan teaches a computer-implemented method for optimizing IC layout yield by using "local design rules" (LDRs) to modify layouts that are bound by conventional "global design rules" (GDRs). Petitioner mapped Allan's process to the steps of independent claim 1: receiving an IC layout (limitation A); receiving descriptions of the manufacturing process, such as design rules derived from process knowledge (limitation B); constructing initial constraints from the GDRs (limitation C); computing local modifications via LDRs (limitation D); constructing new local constraints by combining the LDRs and GDRs (e.g., New Constraint >= LDR + GDR) (limitation E); enforcing these new constraints to adjust the layout (limitations F and G); and thereby producing a new layout with increased yield (limitation H).
  • Motivation to Combine (for §103 grounds): This ground is based on a single reference. Petitioner asserted that even if not fully anticipated, the claims would have been obvious over Allan because any minor differences would have been obvious modifications to a person of ordinary skill in the art (POSITA). Allan's stated purpose is to address the shortcomings of applying GDRs across an entire layout and to increase yield, directly aligning with the problem solved by the ’012 patent.
  • Expectation of Success (for §103 grounds): Petitioner contended a POSITA would have a high expectation of success as Allan explicitly describes a complete system for using LDRs to improve yield, providing a clear roadmap for implementation.

Ground 2: Obviousness over Allan and Kroyan - Claims 4 and 6-9 are obvious over Allan in view of Kroyan.

• Prior Art Relied Upon: Allan (a 1992 IEEE journal article) and Kroyan (Patent 7,523,429).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground supplements Allan with Kroyan to teach the specific methods recited in dependent claims 4 and 6-9. Kroyan discloses techniques to "locally optimize manufacturability" by identifying "weak spots" (processing hotspots) in a layout and applying known modifications. Specifically, Kroyan teaches using a knowledge database (a form of look-up table) of problematic patterns and remedial solutions. Petitioner argued Kroyan explicitly discloses using look-up data tables (claim 9), detecting processing hotspots (claim 6), calculating modifications using simulation models at control points (claim 7), and calculating modifications from simulated printability, including edge placement error (claim 8), all of which are elements of the descriptions of a manufacturing process (claim 4).
  • Motivation to Combine (for §103 grounds): A POSITA would combine Allan and Kroyan because both address the same problem: optimizing IC layouts at a local level where global rules are inefficient. A POSITA would be motivated to implement Allan’s LDR concept using Kroyan’s more systematic approach of a knowledge database (look-up table) to efficiently identify problem areas and store local optimization solutions. This combination represents using a known, efficient data structure (Kroyan's database) to implement a known layout optimization strategy (Allan's LDRs).
  • Expectation of Success (for §103 grounds): A POSITA would have a reasonable expectation of success in combining the references. The combination involves applying Kroyan's known technique for identifying and fixing "weak spots" to Allan's known process for local layout optimization, a predictable integration to improve yield.

4. Key Claim Construction Positions

• "description(s) of manufacturing process" (Claims 1 and 4): Petitioner argued this term should be given its plain and ordinary meaning and should not be limited to requiring all of the examples listed in the specification (e.g., design rules, simulation models, equipment settings). Petitioner supported this by invoking the doctrine of claim differentiation, noting that dependent claim 4 recites a specific list of such descriptions ("design rules, simulation models, equipment settings, material selections, and look-up data tables"). Therefore, independent claim 1 must be broader in scope and does not require all, or even any specific combination, of these elements. This construction is critical to Petitioner's argument that Allan discloses this limitation by teaching the use of design rules and simulation models derived from process knowledge.

5. Relief Requested

• Petitioner requests inter partes review and cancellation of claims 1-11 and 13-14 of the ’012 patent as unpatentable.