Power Integrations Inc v. Semiconductor Components Industries LLC

1. Case Identification

• Case #: IPR2017-01975
• Patent #: RE39,933
• Filed: August 22, 2017
• Petitioner(s): Power Integrations, Inc.
• Patent Owner(s): Semiconductor Components Industries, LLC
• Challenged Claims: 1, 6, 8, 9, 14, 15-17, 19-29, 32-37, 40-43, and 45

2. Patent Overview

• Title: Power Conversion Integrated Circuit and Method for Programming
• Brief Description: The ’933 patent discloses a power conversion integrated circuit featuring a pulse-width modulated (PWM) control circuit and a distinct "state circuit." The state circuit is designed to control the on/off operational modes of a power supply by comparing an external control signal to a reference value and storing the result in a memory circuit, which then generates a mode signal for the PWM control circuit.

3. Grounds for Unpatentability

Ground 1: Anticipation by UC1828 Datasheet - Claims 1, 6, 8, 9, 14, 15-17, 19-29, 32-37, 40-43, and 45 are anticipated under 35 U.S.C. § 102(b) by the [UC1828 Datasheet](https://ai-lab.exparte.com/case/ptab/IPR2017-01975/doc/1004).

• Prior Art Relied Upon: Unitrode UC1828, UC2828, and UC3828 Current Mode PWM Controller IC Datasheet (Unitrode publication, Nov. 1994) ("UC1828 Datasheet").
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that the UC1828 Datasheet, published more than one year before the ’933 patent's priority date, discloses every limitation of the challenged claims. The datasheet describes a monolithic, current-mode PWM controller IC with functionality that directly corresponds to the claimed invention.
    • State Circuit: Petitioner asserted that the UC1828's protection features constitute the claimed "state circuit." This includes a "shutdown comparator" that compares a control signal received on the SHUTDN pin to a fixed 1.5V internal reference signal.
    • Memory Circuit and Mode Signal: The output of this shutdown comparator is coupled to the "S" (SET) input of a "shutdown latch," which Petitioner identified as the claimed "memory circuit." This latch stores the state (on/off) determined by the comparator. The output of the shutdown latch, in conjunction with other logic gates, effectively serves as the claimed "mode signal" that determines whether the PWM controller is enabled or disabled.
    • Control Circuit: The PWM controller section of the UC1828 was identified as the claimed "control circuit." It is responsive to a feedback signal at the F/B pin and produces a pulse-width modulated output signal at the OUT pin to drive a power switch, thereby regulating the power converter's output. The "mode signal" from the state circuit controls this PWM controller, placing it in a shutdown mode of operation where the PWM output is held low.
    • Dependent Claims: Petitioner further contended that the datasheet discloses all limitations of the dependent claims, including specific electrical connections, methods of operation (such as monitoring signals and setting memory states), and brown-out detection via the ENABLE pin functionality.
  • Key Aspects: The central thesis of the petition was that the UC1828 Datasheet describes an integrated circuit with a fault protection scheme (the latched shutdown feature) that performs the exact function of the ’933 patent’s "state circuit." Petitioner emphasized that this prior art was not considered during the original or reissue prosecution, leading the Examiner to allow the claims under the mistaken belief that the claimed architecture was novel and non-obvious.

4. Relief Requested

• Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 1, 6, 8, 9, 14, 15-17, 19-29, 32-37, 40-43, and 45 of Patent RE39,933 as unpatentable.