PTAB

IPR2017-01991

Amazon.com Inc v. Broadcom Corp

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Graphics Accelerator
  • Brief Description: The ’480 patent describes a graphics accelerator on a single integrated circuit. The system features a local memory, a coprocessor for pixel operations, and a direct memory access (DMA) engine for transferring graphics data between an external memory and the local memory, as well as directly to a plurality of processing pipelines to improve performance.

3. Grounds for Unpatentability

Ground 1: Obviousness over Caulk and Kelley - Claims 1, 3-4, 24, 32, 40, 51, 57-58, 63, 80, and 82 are obvious over Caulk in view of Kelley.

  • Prior Art Relied Upon: Caulk (Patent 5,392,391) and Kelley (Patent 5,307,449).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Caulk teaches a high-performance graphics controller on a single integrated circuit that meets most limitations of the independent claims. Caulk's system includes a local memory (Data Cache 18), a coprocessor for graphics operations, and a DMA controller that transfers data between external and local memory. Petitioner contended that the key limitation not explicitly disclosed by Caulk is a plurality of processing pipelines. To address this, Petitioner cited Kelley, which discloses a graphics accelerator with multiple parallel rendering pipelines for accelerating computer graphics.
    • Motivation to Combine: A POSITA would combine Caulk's architecture with Kelley's parallel processing teachings to achieve enhanced performance. Petitioner asserted that parallel rendering was a well-known technique for accelerating graphics processing. A POSITA would have recognized that incorporating Kelley’s parallel pipeline architecture into Caulk's efficient DMA-based system was a predictable and obvious design choice to further increase throughput and reduce bandwidth requirements.
    • Expectation of Success: The combination involved applying known techniques (parallel processing) to a known architecture (a DMA-based graphics accelerator) to achieve a predictable result (improved performance). Therefore, a POSITA would have had a reasonable expectation of success.

Ground 2: Obviousness over Caulk and Kirkland - Claims 25, 27, 38-39, 49-50, and 61-62 are obvious over Caulk in view of Kirkland.

  • Prior Art Relied Upon: Caulk (Patent 5,392,391) and Kirkland (Patent 5,917,502).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground builds on Caulk's disclosures and introduces Kirkland to teach specific features recited in the dependent claims. Petitioner argued that Kirkland, which describes a parallel processing graphics accelerator, explicitly teaches a DMA module with a "queue of transfers and control values" for holding a plurality of DMA commands (addressing claim 27). Kirkland also discloses that various memory types, including SRAM and other forms of RAM, can be used for local memory (addressing claims 25, 38-39, 49-50, 61-62, which require the local memory to be RAM or SRAM).
    • Motivation to Combine: A POSITA would be motivated to add Kirkland's DMA command queue to Caulk's accelerator to maximize the DMA's efficiency and speed up graphics processing by ensuring the DMA is continuously supplied with tasks. Likewise, implementing the local memory in Caulk using SRAM or RAM, as taught by Kirkland, was an obvious choice to improve performance, as fast random-access memory was a well-known and conventional component for high-speed graphics accelerators.
    • Expectation of Success: Implementing a command queue for a DMA controller and using SRAM for local memory were standard, well-understood design choices in the field, ensuring a high expectation of success.

Ground 3: Obviousness over Caulk and Balmer - Claims 43-45, 54-56, and 66-68 are obvious over Caulk in view of Balmer.

  • Prior Art Relied Upon: Caulk (Patent 5,392,391) and Balmer (Patent 5,524,265).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground uses Caulk as a base and introduces Balmer for limitations related to a memory arbiter. Petitioner asserted that Balmer teaches a "transfer controller" that functions as a memory arbiter, which "intelligently queues, sets priorities and services the data requests" from multiple processors. This disclosure directly maps to the claim limitations requiring a memory arbiter that prioritizes memory requests associated with the graphics accelerator and assigns different priorities to different requests.
    • Motivation to Combine: A POSITA would combine Balmer's advanced memory arbiter with Caulk's graphics accelerator to efficiently manage memory access conflicts between the core processor, coprocessor, and DMA engine. Petitioner argued this would reduce delays and improve overall system efficiency, a known benefit of using a dedicated memory arbiter. The ’480 patent itself acknowledges that the design of arbiters for handling requests with different priorities was well-known in the art.
    • Expectation of Success: Integrating a memory arbiter to manage requests from different components was a standard and predictable solution for improving performance in complex integrated circuits, leading to a high expectation of success.

4. Key Claim Construction Positions

  • "processing pipeline": Petitioner proposed this term should be construed as a “set of sequential components for processing data which is organized such that the output of one component becomes the input of the next component.” This construction was central to Petitioner’s argument that Caulk’s single “datapath” constitutes a processing pipeline, thereby allowing it to be combined with prior art that teaches a plurality of such pipelines to render the claims obvious.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1, 3-4, 24-25, 27, 32, 38-40, 43-45, 49-51, 54-58, 61-63, 66-68, 80, and 82 as unpatentable.