PTAB

IPR2017-01994

HP Inc. v. Goodman, James

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1. Case Identification

2. Patent Overview

  • Title: Volatile Memory System with Low-Power Data Retention
  • Brief Description: The ’315 patent discloses a system for retaining data in volatile memory, such as Synchronous Dynamic Random-Access Memory (SDRAM), during low-power conditions. The invention describes using a control device to electrically isolate the memory from address and control busses and place it into a "power down self-refresh mode" to reduce power consumption, with the potential for a secondary backup power source to preserve data during a power failure.

3. Grounds for Unpatentability

Ground 1: Claims 1 and 5 are obvious over Schaefer in view of Qureshi.

  • Prior Art Relied Upon: Schaefer (Patent 5,600,605) and Qureshi (Patent 5,793,776).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that the combination of Schaefer and Qureshi teaches every element of independent claim 1. Schaefer was asserted to disclose a volatile SDRAM memory device (meeting the "plurality of volatile solid state memory devices" limitation) that is capable of entering a low-power, self-refresh mode. Qureshi was asserted to teach a memory controller (the claimed "control device") configured to place such an SDRAM into its self-refresh mode. Petitioner contended that when Qureshi’s controller initiates this mode, the SDRAM inherently ignores all other input signals, thus satisfying the claim limitation of being "electrically isolated" from the address and control lines to reduce power consumption. Dependent claim 5, which requires the memory devices to be DRAM semiconductor microchips, was argued to be obvious because SDRAM is a well-known type of DRAM.
    • Motivation to Combine: A person of ordinary skill in the art (POSITA) would combine the memory controller of Qureshi with the SDRAM of Schaefer because they are complementary functional modules designed for interoperability. Petitioner argued that using a standard controller (Qureshi) to place a compatible memory chip (Schaefer) into a known low-power state was a simple and predictable design choice to achieve the common goal of data retention with reduced power consumption, particularly for testing purposes as described in Qureshi.
    • Expectation of Success: The combination was presented as yielding entirely predictable results. A POSITA would expect that commanding an SDRAM to enter its documented self-refresh mode would cause it to retain data while consuming less power, as this involves using known components for their intended and well-understood functions.

Ground 2: Claims 10 and 16 are obvious over Schaefer in view of Qureshi, and further in view of Mazur.

  • Prior Art Relied Upon: Schaefer (Patent 5,600,605), Qureshi (Patent 5,793,776), and Mazur (Patent 5,204,840).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground incorporated the Schaefer/Qureshi combination from Ground 1 and added Mazur to teach the additional limitations of independent claim 10. Petitioner argued Mazur explicitly remedies the known vulnerability of volatile memory to power failure by teaching a backup power system. Specifically, Mazur was asserted to disclose a "second electrical power source" (a continuously rechargeable battery), a "power loss detection circuit" that senses when the primary voltage drops below a predetermined level (e.g., 4.8V), and a "switch-over circuit." This switch-over circuit was argued to be the claimed "control device" operable for disconnecting the failing primary power source and connecting the secondary battery power to preserve data in the DRAM. Dependent claim 16 (DRAM microchips) was argued to be taught by the combination for the same reasons as claim 5.
    • Motivation to Combine: A POSITA, having already combined Schaefer and Qureshi to create a low-power data retention system, would be motivated to integrate Mazur's teachings to make that system robust against primary power failure. Petitioner contended that protecting volatile memory with a battery backup was a well-known solution to a common problem, and Mazur provided an explicit blueprint for doing so. The motivation would be to enhance the system's reliability and prevent data corruption, an obvious and desirable goal.
    • Expectation of Success: Petitioner asserted that a POSITA would have a high expectation of success in this combination. Adding a standard backup power circuit, as taught by Mazur, to a DRAM memory system is a conventional and well-established engineering practice that would function as expected without requiring undue experimentation.

4. Key Technical Contentions (Beyond Claim Construction)

  • Predictability of the Field and Modularity of Components: A central theme of the petition was that the relevant field of computer memory systems was highly predictable at the time of the alleged invention. Petitioner argued that the prior art references teach modular, functional electronic components (SDRAM chips, memory controllers, power management circuits) that a POSITA would understand could be combined in a "plug and play" manner. This asserted modularity and predictability supported the obviousness combinations, as a POSITA would be able to assemble these known elements to achieve their expected, cumulative functions without any surprising or unexpected results.

5. Relief Requested

  • Petitioner requested the institution of an inter partes review and cancellation of claims 1, 5, 10, and 16 of Patent 6,243,315 as unpatentable under 35 U.S.C. §103.