PTAB

IPR2017-02021

Samsung Electronics America Inc v. Goodman James

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1. Case Identification

2. Patent Overview

  • Title: Volatile Memory System with Self Refresh Mode
  • Brief Description: The ’315 patent discloses a volatile memory system designed to retain data during low-power situations. The system includes a control device that, upon detecting memory inactivity, electrically isolates the memory devices from their address and control lines and places them into a low-power self-refresh mode.

3. Grounds for Unpatentability

Ground 1: Anticipation of Claims 1 and 5 under 35 U.S.C. §102

  • Prior Art Relied Upon: Dell (Patent 6,327,664).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Dell disclosed every limitation of claims 1 and 5. Dell described a memory module with individually addressable SDRAM banks capable of entering a low-power self-refresh mode. Petitioner identified Dell’s memory bus controller (34) in combination with a Field Effect Transistor (FET) switch (52) as the claimed "control device" that selectively isolates the memory devices from the address/control bus. Furthermore, Dell’s system memory controller (28) was identified as the "memory access enable control device" that determines when the memory is inactive and initiates the low-power mode by instructing the bus controller to open the FET switch, thereby isolating the SDRAMs and placing them in self-refresh mode.
    • Key Aspects: This ground asserted that Dell’s disclosure of deactivating memory receivers and using a FET switch to disconnect the address/control bus inherently taught the claimed "electrical isolation" to prevent errant signals.

Ground 2: Obviousness of Claims 10 and 16 under 35 U.S.C. §103

  • Prior Art Relied Upon: Dell (Patent 6,327,664) and Abe (Patent 5,590,082).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground addressed claim 10, which added limitations related to a secondary power source. Petitioner argued Dell taught the base memory system of claim 1, and Abe taught the remaining elements. Abe disclosed a memory control circuit with a main power supply for normal operation and an auxiliary power supply (e.g., a battery) for self-refresh functions when the main power is cut off. Abe’s power supply monitors determined when the main voltage dropped below a predetermined level, triggering a switch to the auxiliary supply.
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSA) would combine Dell and Abe to improve the power efficiency and data integrity of a battery-operated system, a key concern disclosed in Dell. Adding Abe’s power-switching functionality to Dell’s memory isolation system was presented as a combination of known elements to solve the known problem of data loss during power failure, yielding predictable results.
    • Expectation of Success: A POSA would have a reasonable expectation of success because both references addressed DRAM self-refresh modes, and integrating Abe’s power monitoring and switching circuit with Dell’s memory system involved applying a known power-saving technique to a compatible system.

Ground 3: Obviousness of Claims 1 and 5 under 35 U.S.C. §103

  • Prior Art Relied Upon: Ooishi (Patent 6,172,928) and Palaniswami (Patent 6,144,219).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground presented an alternative challenge to claims 1 and 5. Petitioner asserted that Ooishi disclosed a semiconductor memory device with a DRAM unit capable of entering a power-down, self-refresh mode. In this mode, power is cut off to components not required for the self-refresh operation. Palaniswami was argued to supply the explicit "isolation" element, disclosing an "isolation mechanism" situated between a processor and a DRAM controller to prevent data corruption from faulty signals during low-power events.
    • Motivation to Combine: A POSA would be motivated to interpose the known isolation technique from Palaniswami into the low-power memory system of Ooishi. This combination would predictably prevent errant signals from corrupting data in Ooishi's DRAM during its self-refresh mode, a known problem with a known solution. Ooishi itself suggested isolating the DRAM by powering down certain circuits, providing a motivation to use a dedicated isolation mechanism like Palaniswami's for a more robust solution.
    • Expectation of Success: Success was expected as the combination involved integrating a standard isolation circuit (Palaniswami) into a standard DRAM architecture (Ooishi) to achieve the well-understood goal of protecting data integrity.

  • Additional Grounds: Petitioner asserted additional obviousness challenges. Ground 3 argued claims 2-4 and 6-9 are obvious over Dell in view of the JEDEC industry standard (JESD21-C), which provided the claimed connector dimensions and serial presence detect circuitry. Ground 4 argued claims 11-15 and 17-20 are obvious over Dell, Abe, and JESD21-C. Ground 6 argued claims 10 and 16 are obvious over Ooishi, Palaniswami, and Abe. These grounds relied on similar motivations to combine to add industry-standard features or alternative power sources.

4. Key Claim Construction Positions

  • Petitioner dedicated a section to construing the term "selectively electrically isolating said memory devices from respective address lines and respective control lines."
  • Petitioner argued this term should be given its plain and ordinary meaning under the broadest reasonable construction standard, which is to "inhibit signals from arriving at the given memory devices." This construction was supported by the patent’s claim language and specification, which stated that when isolated, signals on the address and control lines "do not reach said memory devices" in order to prevent "errant signals" from affecting retained data.

5. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1-20 of the ’315 patent as unpatentable.