PTAB

IPR2018-00012

Samsung Electronics Co., Ltd. v. Ibex PT Holdings Co., Ltd.

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1. Case Identification

  • Patent #: 8,654,855
  • Filed: October 4, 2017
  • Petitioner(s): Samsung Electronics Co., Ltd.
  • Patent Owner(s): IBEX PT Holdings Co., Ltd.
  • Challenged Claims: 1-5

2. Patent Overview

  • Title: Apparatus and Method for Decoding Motion Information in Merge Mode
  • Brief Description: The ’855 patent describes an apparatus for decoding video data according to a video compression standard (e.g., HEVC/H.265). The invention focuses on efficiently decoding motion information for a "current block" of a video frame by using a "merge mode," which allows the current block to inherit motion information from neighboring spatial or temporal candidate blocks.

3. Grounds for Unpatentability

Ground 1: Obviousness over WD4-v2, Lin, and Zhou II - Claims 1-5 are obvious over WD4-v2 in view of Lin and Zhou II.

  • Prior Art Relied Upon:
    • WD4-v2 (JCTVC-F803, version 2: a working draft of the High-Efficiency Video Coding standard)
    • Lin (Application # 2012/0236942)
    • Zhou II (JCTVC-F081, version 2: a technical proposal for the HEVC standard)
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that the combination of references teaches all limitations of the challenged claims.
      • WD4-v2, as a primary reference and a working draft of the HEVC standard, was alleged to disclose the core elements of the claimed decoding apparatus. This included the three main functional units of claim 1, construed as means-plus-function limitations: a “merge mode motion information decoding unit,” a “prediction block generation unit,” and a “residual block decoding unit.” Petitioner contended that WD4-v2 describes the underlying processes for these units, such as using spatial and temporal candidates, reconstructing a merge predictor index from a codeword, generating prediction blocks via interpolation, and decoding residual blocks through inverse scanning, inverse quantization, and inverse transformation.
      • Lin was cited to teach that it was well-known and obvious to implement such video decoding processes on a general-purpose processor, microprocessor, or Digital Signal Processor (DSP), thereby satisfying the "processor programmed to..." structure required by the means-plus-function construction.
      • Zhou II was introduced to supply a specific limitation of claim 1(e) not explicitly found in WD4-v2. Specifically, Zhou II allegedly discloses selecting the motion vector of a second temporal merge candidate block when the current block is adjacent to a lower boundary of the largest coding unit (LCU). This addresses the final limitation of independent claim 1.
      • Dependent claims 2-5 were argued to be obvious as they recite additional, known features of HEVC-style video coding also disclosed in WD4-v2, such as using a single quantization parameter (QP) for coding units above a certain size and predetermining reference sizes per picture or slice.
    • Motivation to Combine:
      • A person of ordinary skill in the art (POSITA) would combine WD4-v2 and Lin because implementing a standard’s specified algorithms (WD4-v2) on a known processor (Lin) is a common and predictable way to create a functional video decoder.
      • A POSITA would be motivated to incorporate the teachings of Zhou II into the system of WD4-v2 because both documents relate to the same HEVC standard development process and address similar technical challenges. Zhou II was presented as an alternative solution to improve memory bandwidth for temporal motion vector prediction, making its adoption a predictable design choice to enhance the efficiency of the WD4-v2 framework.
    • Expectation of Success: Petitioner asserted a POSITA would have had a reasonable expectation of success in combining the references. All three relate to the same technical field of HEVC video coding, and Zhou II was specifically proposed for incorporation into the HEVC working draft, ensuring its compatibility with the processes described in WD4-v2.

4. Key Claim Construction Positions

  • Petitioner’s arguments relied heavily on the means-plus-function construction for the three "unit" limitations in claim 1, which was adopted from the Board's decision in the prior, related IPRs (IPR2017-00101 and IPR2017-00102).
  • “merge mode motion information decoding unit”: This term was construed as "a processor programmed to implement the processes performed by (i) blocks 231-238 of Figure 5, (ii) blocks 331-337 of Figure 6, or (iii) blocks 431-438 of Figure 7, or equivalents thereof." Petitioner adopted this construction for the petition.
  • “prediction block generation unit” and “residual block decoding unit”: These terms were similarly construed as a processor programmed to implement the corresponding algorithms and processes disclosed in the ’855 patent specification (e.g., unit 250 and unit 260 of Fig. 4).

5. Key Technical Contentions (Beyond Claim Construction)

  • Prior Art Status of References: A central contention was that WD4-v2 and Zhou II qualify as "printed publications" under 35 U.S.C. §102. Petitioner provided extensive evidence, including expert declarations from Mr. Bross (an author of WD4-v2) and Dr. Vetro, arguing these documents were made publicly available on specific dates (July 11, 2011, for Zhou II and August 9, 2011, for WD4-v2) via the JCT-VC and MPEG document management websites and email reflectors, accessible to hundreds of interested members and the public.
  • Effective Filing Date: Petitioner argued that the challenged claims were not entitled to the ’855 patent’s claimed foreign priority date (August 29, 2011). It contended the Korean priority application failed to provide adequate written support for the limitation in claim 1(e) regarding the selection of a motion vector when a block is adjacent to a lower boundary of a coding unit. Therefore, the critical date for prior art was argued to be the PCT filing date of January 20, 2012, rendering WD4-v2 and Zhou II valid prior art.

6. Arguments Regarding Discretionary Denial

  • The petition was a "follow-on" petition filed after two previous petitions on the same patent were denied institution. Petitioner dedicated significant argument to why the Board should not exercise discretionary denial under 35 U.S.C. §314(a).
  • The core argument was that this petition was not an attempt to correct prior deficiencies or present new arguments based on Patent Owner feedback. Instead, Petitioner explicitly adopted the Board’s own claim construction from the prior denials and applied the exact same prior art combination. Because the Patent Owner did not file a preliminary response in the earlier cases, Petitioner argued it was not gaining an unfair advantage but was diligently seeking a ruling on the merits under the Board's interpretation of the claims.

7. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1-5 of the ’855 patent as unpatentable under 35 U.S.C. §103.