ASUS Computer International, Inc. v. Fink, David

1. Case Identification

• Case #: IPR2018-00047
• Patent #: 6,243,315
• Filed: October 12, 2017
• Petitioner(s): ASUS Computer International, Inc..
• Patent Owner(s): James Goodman
• Challenged Claims: 1-20

2. Patent Overview

• Title: Memory System with Low-Power Data Retention
• Brief Description: The ’315 patent discloses a volatile memory system designed to retain data during low-power situations. The system features a control device that can selectively isolate solid-state memory devices (e.g., DRAM) from their address and control lines and place them into a self-refresh mode to reduce power consumption when not being accessed. The patent also describes using a secondary electrical power source to preserve data when the primary power source fails.

3. Grounds for Unpatentability

Ground 1: Anticipation of Claims 1 and 5 - Claims 1 and 5 are anticipated by Dell under 35 U.S.C. §102.

• Prior Art Relied Upon: Dell (Patent 6,327,664).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Dell discloses every element of independent claim 1. Dell teaches a memory module with synchronous DRAMs (SDRAMs) capable of operating in several reduced power modes, including a self-refresh mode. Dell’s bus controller, in conjunction with a Field-Effect Transistor (FET) switch, serves as the claimed "control device" by disconnecting the address and control bus from the SDRAMs, thereby "electrically isolating" them. Furthermore, Dell’s system memory controller acts as the "memory access enable control device" by determining when the memory is not being accessed and initiating the low-power mode. Petitioner asserted that dependent claim 5 is also anticipated because Dell explicitly discloses that its memory devices are DRAM semiconductor microchips.

Ground 2: Obviousness of Claims 10 and 16 - Claims 10 and 16 are obvious over Dell in view of Abe.

• Prior Art Relied Upon: Dell (Patent 6,327,664), Abe (Patent 5,590,082).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that Dell provides the base system for claim 10, including the isolating control device and self-refresh mode, while Abe teaches the remaining elements related to a secondary power source. Abe describes a memory control circuit for a DRAM system that includes both a main power supply and an auxiliary power supply (e.g., a battery). Abe’s circuit monitors the main voltage and automatically switches to the auxiliary supply to power self-refresh operations if the main voltage falls below a predetermined threshold.
  • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine Dell’s power-saving isolation architecture with Abe’s backup power-switching functionality. Both references address power management in DRAM systems. A POSITA would be motivated to integrate Abe’s solution to solve the known problem of data loss from unexpected power failure or battery depletion, an issue particularly relevant to the battery-operated systems mentioned in Dell.
  • Expectation of Success: The combination involved applying Abe’s known power-switching technique to Dell's known memory system. This represented a simple substitution of known elements to achieve the predictable result of enhanced data integrity during main power loss, posing no significant technical challenges.

Ground 3: Obviousness of Claims 1 and 5 - Claims 1 and 5 are obvious over Ooishi in view of Palaniswami.

• Prior Art Relied Upon: Ooishi (Patent 6,172,923), Palaniswami (Patent 6,144,219).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner presented this as an alternative challenge to claims 1 and 5. Ooishi discloses a base DRAM memory device with a self-refresh control circuit that reduces power consumption by de-powering non-essential circuitry during a power-down mode. Palaniswami explicitly teaches an "isolation mechanism" placed between a digital signal processor (DSP) and a DRAM controller. The stated purpose of Palaniswami's mechanism is to prevent faulty signals, which can occur during low-power conditions, from reaching and corrupting the DRAM.
  • Motivation to Combine: A POSITA would be motivated to incorporate the dedicated isolation mechanism of Palaniswami into the memory system of Ooishi. This combination would predictably prevent errant signals from corrupting data stored in Ooishi's DRAM during its low-power self-refresh mode. Palaniswami's teaching that its isolation feature can be employed in other systems would have encouraged this integration.
  • Expectation of Success: As both references relate to controlling DRAM in low-power situations, a POSITA would have reasonably expected that integrating Palaniswami's known isolation technique into Ooishi's system would successfully and predictably result in a more robust memory system.

• Additional Grounds: Petitioner asserted additional obviousness challenges, including combining Dell with the JESD21-C standard to teach dependent claims related to standard connectors (e.g., DIMM, SODIMM) and serial presence detect circuitry (Ground 3), and further combining Dell, Abe, and JESD21-C to cover other dependent claims (Ground 4). An alternative ground for claims 10 and 16 combined Ooishi, Palaniswami, and Abe (Ground 6).

4. Key Claim Construction Positions

• "selectively electrically isolating said memory devices from respective address lines and respective control lines": Petitioner argued this term, given its plain and ordinary meaning in light of the specification, should be construed to mean inhibiting signals from arriving at the memory devices. This construction was central to Petitioner's argument, as it allowed prior art that disclosed disconnecting or de-powering signal pathways via switches or other means to meet this claim limitation by preventing "errant signals" from affecting the memory chips.

5. Relief Requested

• Petitioner requested the institution of an inter partes review and the cancellation of claims 1-20 of Patent 6,243,315 as unpatentable under 35 U.S.C. §§ 102 and 103.