PTAB

IPR2018-00047

ASUS Computer Intl Inc v. Fink David

Log In
Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Volatile Memory System with Low-Power Data Retention
  • Brief Description: The ’315 patent describes a memory system for a computer that includes volatile memory devices (e.g., DRAM). The system features a control device that can selectively isolate the memory devices from address and control lines and place them into a low-power, self-refresh mode to retain data when the memory is not being accessed.

3. Grounds for Unpatentability

Ground 1: Anticipation of Claims 1 and 5 under §102

  • Prior Art Relied Upon: Dell (Patent 6,327,664).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Dell disclosed every limitation of claims 1 and 5. Dell described a memory module with multiple synchronous DRAMs (SDRAMs) capable of operating in several low-power modes, including a self-refresh mode. Petitioner contended that Dell’s bus controller (34) in conjunction with a FET switch (52) constituted the claimed “control device” that selectively electrically isolated the SDRAMs from the address and control bus. Furthermore, Dell’s system memory controller (28) served as the “memory access enable control device” by determining when the memory was not being accessed and initiating a low-power mode. In this mode, the control device opened the FET switch to isolate the SDRAMs and place them in self-refresh mode, thereby reducing power consumption. For dependent claim 5, Dell’s disclosure of using SDRAMs met the limitation of “DRAM semiconductor microchips.”

Ground 2: Obviousness of Claims 10 and 16 under §103

  • Prior Art Relied Upon: Dell (Patent 6,327,664) and Abe (Patent 5,590,082).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Dell taught the base memory system with isolation, as described in Ground 1. Abe taught a memory control circuit designed to preserve DRAM data during power fluctuations. Abe disclosed a system with a first (main) power supply and a second (auxiliary/backup) power source. Abe’s power supply monitors detected when the voltage from the main supply fell below a predetermined level and, in response, used diodes to switch power to the auxiliary source, which then maintained the DRAM in self-refresh mode.
    • Motivation to Combine: A person of ordinary skill in the art (POSA) would combine Abe’s power-switching functionality with Dell’s memory isolation system to solve the known and critical problem of data loss when a computer’s main power source fails or is depleted. Both references address power efficiency and data retention in DRAM systems. Adding Abe’s backup power circuit to Dell’s system was argued to be a simple substitution of known elements to improve the system’s robustness, yielding predictable results.
    • Expectation of Success: A POSA would have had a high expectation of success, as combining known power monitoring and backup battery circuits with known DRAM systems was a common and well-understood practice in the art to prevent data loss.

Ground 5: Obviousness of Claims 1 and 5 under §103

  • Prior Art Relied Upon: Ooishi (Patent 6,172,928) and Palaniswami (Patent 6,144,219).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued that Ooishi disclosed a memory device with a self-refresh mode that reduced power consumption by cutting power to all circuitry not required for the self-refresh operation. This de-powering of components, such as those that route address and control signals, inherently provided electrical isolation. Palaniswami taught a dedicated “isolation mechanism” to be placed between a processor and a DRAM controller. The explicit purpose of this mechanism was to selectively isolate the DRAM from signals coming from the processor upon the occurrence of a low-power condition, thereby preventing data corruption from faulty or errant signals.
    • Motivation to Combine: A POSA would have been motivated to incorporate Palaniswami’s explicit isolation mechanism into Ooishi’s memory system. While Ooishi’s system inherently isolated the memory by cutting power, adding Palaniswami’s dedicated circuit would provide a more robust and direct method of preventing errant signals from corrupting data. This combination applied a known technique (explicit signal isolation) to a known system (a DRAM with self-refresh) to achieve the predictable result of enhanced data integrity.
    • Expectation of Success: Interposing a known isolation circuit like that in Palaniswami into the signal path of a memory system like Ooishi’s would have posed no significant technical challenges and would have been expected to function as intended.

  • Additional Grounds: Petitioner asserted additional obviousness challenges for various dependent claims based on combinations including Dell, Abe, and JESD21-C (an industry standard for memory module configurations). Another ground challenged claims 10 and 16 over the three-way combination of Ooishi, Palaniswami, and Abe.

4. Key Claim Construction Positions

  • Petitioner argued that the term “selectively electrically isolating said memory devices from respective address lines and respective control lines” should be construed according to its plain and ordinary meaning, which refers to inhibiting signals from arriving at the memory devices. This construction was central to Petitioner’s arguments, as the prior art disclosed preventing errant signals via methods like opening FET switches (Dell) or de-powering input circuitry (Ooishi), which functionally inhibit signals from reaching the memory cells.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-20 of the ’315 patent as unpatentable under 35 U.S.C. §§ 102 and 103.