PTAB

IPR2018-00101

MediaTek Inc v. ATI Technologies ULC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Parallel Pipeline Graphics System
  • Brief Description: The ’506 patent discloses a graphics processing system, preferably on a single chip, that uses a front-end to process graphics instructions into geometry and a back-end with multiple parallel pipelines to process that geometry into final pixels. The pipelines incorporate features like "unified shaders," screen tiling, and various forms of z-buffering for visibility testing.

3. Grounds for Unpatentability

Ground 1: Obviousness over Akeley and Rich - Claims 1-3 and 5-9 are obvious over Akeley in view of Rich.

  • Prior Art Relied Upon: Akeley (a 1993 article titled "Reality Engine Graphics") and Rich (Patent 5,808,690).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Akeley, a well-known graphics system, disclosed the core architecture of the ’506 patent, including a front-end for geometry processing and a back-end with multiple parallel pipelines. Akeley’s pipelines used "Fragment Generators" that functioned as unified shaders (performing both color and texture shading) and "Image Engines" that performed z-buffering. Rich disclosed a single-chip graphics processor architecture using flexible, programmable Arithmetic Logic Units (ALUs) arranged in parallel panels (pipelines) that performed the same functions as Akeley's system, including rasterization, shading, and tiling. Petitioner contended that combining these references taught all limitations of the challenged claims, including the parallel pipelines, unified shaders, z-buffer logic, and tiling (directing geometry to specific pipelines based on screen location).
    • Motivation to Combine: Petitioner asserted Rich explicitly taught implementing the functionality of prior art parallel graphics systems, such as Akeley's Reality Engine, on a single integrated chip. The goal was to reduce hardware, increase processing speed, and improve efficiency by replacing separate processors on a board with flexible ALUs on a chip. A POSITA would combine the known high-performance architecture of Akeley with the single-chip implementation method of Rich to achieve these predictable benefits. The functional similarity between Akeley's flexible processors and Rich's flexible ALUs would have made the combination intuitive.
    • Expectation of Success: A POSITA would have had a high expectation of success because the combination involved implementing known functionalities (from Akeley) using a known, suitable hardware architecture (from Rich) to achieve predictable improvements in size and performance.

Ground 2: Obviousness over Akeley, Rich, and Greene - Claim 4 is obvious over Akeley in view of Rich in further view of Greene.

  • Prior Art Relied Upon: Akeley ("Reality Engine Graphics" article), Rich (Patent 5,808,690), and Greene (Patent 6,646,639).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon the Akeley and Rich combination from Ground 1 to address the specific limitations of claim 4, which required the z-buffer logic unit to interface with a scan converter through a "hierarchical Z-interface" and an "early Z-interface." While Rich taught a system could be z-buffered and perform visibility testing prior to shading (disclosing an early z-interface), it did not detail the specific type of z-buffering. Petitioner argued that Greene supplied this missing element by disclosing various efficient z-buffering algorithms, including hierarchical z-buffering that performs coarse-level visibility testing before proceeding to finer levels, suitable for hardware implementation.
    • Motivation to Combine: A POSITA implementing the Akeley/Rich single-chip graphics system would be motivated to use an efficient z-buffering method to improve performance. Greene explicitly discussed the need for efficient z-buffering in hardware and described hierarchical techniques as more efficient and suitable for hardware implementation than prior methods. A POSITA would therefore look to a reference like Greene to implement a specific, optimized z-buffering scheme in the combined Akeley/Rich architecture.
    • Expectation of Success: Because Greene described hierarchical z-buffering as a well-known technique for improving efficiency in hardware-implemented graphics systems, a POSITA would have reasonably expected to successfully integrate it into the single-chip system of Akeley and Rich.

4. Key Claim Construction Positions

  • "Z-Buffer Logic Unit" (claims 3-5): Petitioner proposed this term be construed as "a logic unit that facilitates visibility testing by comparing depth values." This broad construction was argued to encompass the "Image Engines" of Akeley and the visibility information calculation units in Rich.
  • "Hierarchical Z-Interface" (claim 4): Petitioner proposed this term be construed as "an interface with a z-buffer logic unit that provides for visibility testing at a coarse level, including, for example, for an entire tile or primitive." This construction was based on the ’506 patent’s disclosure of performing initial, coarse-level stepping to reject entire tiles if possible.
  • "Early Z-interface" (claim 4) / "Late Z-interface" (claim 5): Petitioner proposed "Early Z-interface" be construed as providing "visibility testing prior to shading and texturing" and "Late Z-interface" as providing "visibility testing after shading and texturing." These constructions were based on the patent's explicit description of performing z-buffering "early" to minimize work for the shader or "late" if the shader might modify pixel visibility.

5. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1-9 of the ’506 patent as unpatentable.