PTAB

IPR2018-00180

Power Integrations, Inc. v. Semiconductor Components Industries, LLC

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1. Case Identification

2. Patent Overview

  • Title: Power Converter Circuit and Method for Controlling
  • Brief Description: The ’221 patent discloses switched-mode power supply circuits designed to improve efficiency under low-load conditions. The technology centers on a controller circuit that uses pulse-width modulation (PWM) to regulate output voltage. The purported invention is a "duty cycle detector circuit" that monitors a feedback error signal. When this signal indicates that the converter is operating at or near a minimum duty cycle (i.e., under a light load), the detector asserts a signal that inhibits the PWM output, causing the power supply to skip switching cycles and thereby reduce its power consumption.

3. Grounds for Unpatentability

Ground 1: Anticipation over Hwang - Claims 4-7, 9, and 15-17 are unpatentable under 35 U.S.C. § 102 as anticipated by Hwang.

  • Prior Art Relied Upon: Hwang (Patent 5,747,977).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Hwang teaches every limitation of the challenged claims. Hwang discloses a switching regulator featuring a low-power mode that employs voltage-mode PWM control. Central to the argument, Hwang includes a light load detector (comparator 52) that is functionally identical to the ’221 patent's detector. This comparator receives a feedback error signal (VEAO) and compares it to a predetermined light-load threshold voltage (2V). When the load becomes light and the VEAO signal drops below this threshold, Hwang's circuit disables the switching pulses to conserve power. Petitioner asserted this is a direct teaching of the claimed concept: detecting when a feedback signal crosses a threshold corresponding to a predetermined duty cycle and, in response, disabling the drive signal. Petitioner also mapped elements of dependent claims, noting that Hwang’s Figure 5 discloses the regulator components recited in claim 5, including an oscillator (12), a PWM comparator (50), and a memory storage device (flip-flop 58).

Ground 2: Obviousness over Balakrishnan and Hwang - Claims 9-14 and 18 are obvious over Balakrishnan in view of Hwang.

  • Prior Art Relied Upon: Balakrishnan (Patent 5,313,381) and Hwang (Patent 5,747,977).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Balakrishnan discloses a compact, cost-effective, three-pin integrated circuit for a switched-mode power supply that combines power and feedback signals on a single pin. While Balakrishnan teaches a form of cycle skipping, Petitioner contended its implementation is inefficient at very light loads because it can result in a partial, incomplete turn-on of the power transistor, which wastes power. Hwang, as established in Ground 1, provides the solution: an efficient and precise cycle-skipping mechanism that uses a dedicated comparator and a well-defined threshold to cleanly disable switching pulses entirely.
    • Motivation to Combine: A person of ordinary skill in the art (POSITA) would be motivated to improve the light-load efficiency of Balakrishnan's cost-effective integrated circuit by incorporating Hwang's superior cycle-skipping technique. The objective was to combine the benefits of Balakrishnan's compact, low-pin-count design with the improved efficiency and reliability of Hwang's threshold-based pulse-skipping logic, thereby creating a more robust and efficient power supply controller.
    • Expectation of Success: A POSITA would have had a high expectation of success. The proposed combination involved integrating standard, well-understood circuit blocks (Hwang's comparator and logic gate) into the known architecture of Balakrishnan's controller. This modification was presented as a straightforward application of a known technique (Hwang's method) to improve a similar device (Balakrishnan's circuit), a task well within the ordinary skill in the art.

Ground 3: Anticipation over Harris - Claims 7, 9, 15, 16, and 18 are unpatentable under 35 U.S.C. § 102 as anticipated by Harris.

  • Prior Art Relied Upon: Harris (Harris Semiconductor Application Note AN9212.1).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that the Harris application note, which describes the HIP5060 integrated circuit, fully anticipates the challenged claims. Harris discloses a "burst mode" operation for light-load conditions that is functionally identical to the cycle skipping of the ’221 patent. The HIP5060 circuit contains a "LOW LOAD" comparator that continuously monitors an error amplifier's output voltage (VCMP). If the VCMP signal drops below a defined low-load threshold, the comparator outputs a signal that stops the switching. Switching only resumes once the load increases and the VCMP signal rises back above the threshold. Petitioner asserted this mechanism—a detector that compares a feedback signal to a threshold to disable switching—is a direct anticipation of the claimed invention.
    • Key Aspects: Although Harris describes a current-mode control architecture, which differs from the voltage-mode control described in the ’221 patent, Petitioner argued that the specific cycle-skipping mechanism itself is independent of the control mode and functions identically to what is claimed.

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 4-7 and 9-18 of Patent 6,597,221 as unpatentable.