PTAB

IPR2018-00303

SK Hynix Inc v. Netlist Inc

Log In

1. Case Identification

2. Patent Overview

  • Title: Memory Module Capable of Handshaking with a Memory Controller of a Host System
  • Brief Description: The ’623 patent discloses a memory module that uses a handshaking protocol to communicate the status of an initialization sequence to a host system’s memory controller. This replaces prior art methods of waiting a predetermined time, using a shared open-drain output to signal completion or report errors from multiple modules on a single line.

3. Grounds for Unpatentability

Ground 1: Obviousness over Hazelzet - Claims 1-29 are obvious over Hazelzet

  • Prior Art Relied Upon: Hazelzet (Application # 2008/0098277).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Hazelzet taught every limitation of the challenged claims. Hazelzet disclosed a memory module with an ECC/Parity register (the claimed “module controller”) that operates in two distinct modes: a “parity mode” (the claimed “first mode”) and an “ECC mode” (the claimed “second mode”). Hazelzet’s module controller used an open-drain output (/ERROR (UE)) to report uncorrectable errors to the host memory controller. Petitioner contended that in parity mode, this signal functions as the claimed “parity error signal,” and in ECC mode, it functions as the claimed “notification signal” indicating the status of an error correction sequence, which Petitioner asserted a POSITA would understand to be a type of “training sequence.”
    • Motivation to Combine (for §103 grounds): Not applicable, as this is a single-reference ground. Petitioner contended Hazelzet alone rendered the claims obvious.
    • Expectation of Success (for §103 grounds): Not applicable.

Ground 2: Obviousness over Hazelzet and Amidi - Claims 1-29 are obvious over Hazelzet in view of Amidi

  • Prior Art Relied Upon: Hazelzet (Application # 2008/0098277) and Amidi (Application # 2008/0155378).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground was presented as an alternative in case the Board found Hazelzet’s error correction sequence was not a “training sequence.” Amidi was introduced for its explicit teaching of a memory system “training mode” where a memory controller learns to identify and avoid bad memory locations based on error signals from the memory module. Amidi’s training involves the module sending a notification signal to the controller indicating the training status after performing error checking.
    • Motivation to Combine (for §103 grounds): A POSITA would combine Hazelzet with Amidi to improve overall system reliability. Hazelzet taught the benefits of error correction, and Amidi taught a specific training method to make error correction more robust by identifying and mapping out bad memory locations. Combining Amidi’s training scheme with Hazelzet’s dual-mode, open-drain reporting architecture was argued to be a predictable combination of known elements for a known purpose.
    • Expectation of Success (for §103 grounds): A POSITA would have an expectation of success because both references operated in the same field of memory error correction and used compatible signaling (e.g., open-drain outputs), making the integration straightforward.

Ground 3: Obviousness over Hazelzet and Buchmann - Claims 1-29 are obvious over Hazelzet in view of Buchmann

  • Prior Art Relied Upon: Hazelzet (Application # 2008/0098277) and Buchmann (Patent 8,139,430).

  • Core Argument for this Ground:

    • Prior Art Mapping: Similar to the Amidi ground, this combination was asserted to cure any perceived deficiency in Hazelzet’s disclosure of a “training” sequence. Buchmann disclosed a memory system with two modes: a high-speed mode and a low-speed “SBC mode.” The SBC mode was explicitly used for executing initialization and training sequences, during which the memory module generated and output notification signals to the memory controller indicating the status of the training.
    • Motivation to Combine (for §103 grounds): A POSITA would be motivated to incorporate Buchmann’s explicit training protocols into Hazelzet’s system to enhance initialization reliability, particularly for high-speed buses, a problem addressed by both references. Buchmann’s use of a shared bus for notification signals was compatible with Hazelzet’s open-drain architecture, making the combination a simple application of known techniques to improve performance.
    • Expectation of Success (for §103 grounds): Success was expected because implementing Buchmann’s training logic within Hazelzet’s existing error-correcting framework was a predictable design choice that would leverage the strengths of both systems without modification.

  • Additional Grounds: Petitioner asserted additional obviousness challenges, including combining Hazelzet with Talbot (Application # 2008/0147897) to further support the teaching of a training mode. Other combinations included adding Hokenmaier (Patent 7,525,860) for its detailed teachings on open-drain circuit design or Kim (Patent 8,359,521) for its teachings on using a shared error pin with OR-gate logic.

4. Key Claim Construction Positions

  • "mode": Petitioner argued this term required no special construction beyond its plain and ordinary meaning, or alternatively could be construed as “state.” This position was taken to counter a potentially narrower construction of “a distinct behavioral state that a system may be switched to,” which Patent Owner had previously proposed in a related IPR for the parent ’837 patent.
  • "notification signal": Petitioner contended that under the broadest reasonable construction, this term would include signals sent in response to polling as well as those sent without polling. Petitioner argued that the prior art disclosed a notification signal that met the claim limitations regardless of whether polling was included or excluded from the term’s scope.
  • "training": Petitioner advocated for a broad construction that would include not only the training of a memory module but also the training of a memory system or memory controller. This position was supported by citing Patent Owner's own arguments in a related International Trade Commission (ITC) proceeding.

7. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1-29 of Patent 9,535,623 as unpatentable.