PTAB

IPR2018-00303

SK hynix Inc. v. Netlist, Inc.

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1. Case Identification

2. Patent Overview

  • Title: Memory Module Capable of Handshaking with a Memory Controller of a Host System
  • Brief Description: The ’623 patent discloses a memory module designed to communicate its initialization status to a host memory controller using a handshaking protocol. This protocol purportedly improves upon prior art systems, which waited a fixed time, by using a dedicated notification signal on a shared, open-drain output to confirm when initialization sequences are complete.

3. Grounds for Unpatentability

Ground 1: Obviousness over Hazelzet - Claims 1-29 are obvious over Hazelzet.

  • Prior Art Relied Upon: Hazelzet (Application # 2008/0098277).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Hazelzet discloses all key limitations of the independent claims. Hazelzet’s memory module contained an "ECC/Parity register" (the claimed "module controller") which allows operation in two distinct modes: a "parity mode" (first mode) and an "ECC mode" (second mode). It used a single, shared open-drain output pin (/Error (UE)) to report errors in both modes. Petitioner contended this pin drives the claimed "parity error signal" in the first mode and the "notification signal" (an uncorrectable error report) in the second mode.
    • Motivation to Combine (for §103 grounds): As a single-reference obviousness challenge under 35 U.S.C. §103, Petitioner argued that a POSITA would have been motivated to use Hazelzet's existing error detection and correction functionality ("ECC mode") as a "training sequence." This modification was presented as a known technique for the known purpose of improving system reliability by identifying and correcting issues before normal operation.
    • Expectation of Success (for §103 grounds): A POSITA would have had a high expectation of success, as using an error correction process for training would predictably improve the overall reliability and performance of Hazelzet’s system.

Ground 2: Obviousness over Hazelzet and Amidi - Claims 1-29 are obvious over Hazelzet in view of Amidi.

  • Prior Art Relied Upon: Hazelzet (Application # 2008/0098277), Amidi (Application # 2008/0155378).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground was presented as an alternative in case Hazelzet was found not to explicitly teach a "training" sequence. Hazelzet provides the foundational system with dual-mode operation and a shared open-drain output. Amidi was cited for its explicit teaching of a training mode where a memory controller identifies and marks "a bad memory location" to avoid using it in the future, thereby improving system performance.
    • Motivation to Combine (for §103 grounds): A POSITA would combine Hazelzet with Amidi to enhance the reliability of Hazelzet's memory system, a goal explicitly stated in Hazelzet. Because both references operate in the analogous art of memory error correction, incorporating Amidi's known training method into Hazelzet's system was argued to be a predictable combination of known elements for their intended purposes.
    • Expectation of Success (for §103 grounds): A POSITA would reasonably expect success because the combination involves applying Amidi's established training technique to Hazelzet's similar error-correcting architecture to achieve the predictable outcome of enhanced system reliability.

  • Additional Grounds: Petitioner asserted additional obviousness challenges against all or certain claims by combining Hazelzet with other references. These combinations were proposed as alternatives, with Talbot (Application # 2008/0147897) and Buchmann (Patent 8,139,430) providing explicit training sequences, Hokenmaier (Patent 7,525,860) teaching specific open-drain transistor configurations, and Kim (Patent 8,359,521) disclosing the use of a shared open-drain pin to create a wired-OR logic function for error reporting from multiple components.

4. Key Claim Construction Positions

  • "mode": Petitioner contended that "mode" should be given its plain and ordinary meaning, or be construed simply as "state." This position was taken to reject a narrower construction ("a distinct behavioral state that a system may be switched to") that Patent Owner had previously proposed in a related IPR concerning the parent ’837 patent.
  • "notification signal": Petitioner argued that the broadest reasonable construction must include signals indicating status either in response to polling or without polling. This construction was important to counter potential arguments that the patent disparages polling, thereby ensuring that prior art using polled status updates (like Talbot) would remain applicable.
  • "training": Petitioner asserted that "training" is not limited to the memory module alone but broadly includes training of the entire memory system, including the memory controller. This broad construction, based on Patent Owner's own positions in a related International Trade Commission (ITC) proceeding, was critical for applying prior art like Buchmann, which describes training of the high-speed bus, not just the memory module.
  • "indicating ... status": Petitioner argued this term should be construed broadly to include "providing information that can be used to determine the status later," rather than being limited to providing a pre-determined status. This was important for applying prior art where the controller performs the final status determination based on raw data received from the module.

5. Relief Requested

  • Petitioner requested that the Board institute an inter partes review and cancel claims 1-29 of Patent 9,535,623 as unpatentable.