Dell Inc v. Alacritech Inc

1. Case Identification

• Case #: IPR2018-00336
• Patent #: 7,124,205
• Filed: December 20, 2017
• Petitioner(s): Dell Inc.
• Patent Owner(s): Alacritech, Inc.
• Challenged Claims: 3, 9-10, 16, 22, 24-30, 35-36

2. Patent Overview

• Title: Network Interface Device That Fast-Path Processes Solicited Session Layer Read Commands
• Brief Description: The ’205 patent describes a system for accelerating network data transfers by offloading protocol processing from a host computer to a network interface device (NIC). The NIC is designed to perform "fast-path" processing on certain incoming data packets, bypassing the host computer's conventional protocol stack to reduce CPU load and improve system performance.

3. Grounds for Unpatentability

Ground 1: Obviousness over Thia and Satran - Claims 3, 9-10, 16, 22, 27-30, and 35-36 are obvious over Thia in view of Satran.

• Prior Art Relied Upon: Thia (a 1995 academic paper titled “A Reduced Operation Protocol Engine (ROPE) for a Multiple-layer Bypass Architecture”) and Satran (two 2000 Internet Drafts collectively defining the iSCSI protocol).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Thia disclosed the core architecture of the challenged claims, including a host computer with a standard multi-layer protocol stack and a network interface device capable of performing “fast-path” processing. Thia’s system uses a specialized “ROPE” chip on the network adapter to analyze incoming packet headers; if a packet matches a predicted template, it is processed on the adapter, bypassing the host's network and transport protocol layers. Petitioner asserted that Satran supplied the missing element: a specific session-layer protocol (iSCSI) that includes the claimed "solicited read command." The petition contended the combination of Thia’s hardware architecture and Satran’s protocol met the limitations of the independent claims.
  • Motivation to Combine: A POSITA would combine Thia's efficient bypass architecture with Satran's well-known iSCSI protocol to create a practical, high-performance system. The petition asserted several motivations: providing Thia's hardware with a real-world communications protocol, improving functionality by enabling network storage access, reducing the host's workload, and broadening the system's market appeal. This motivation was allegedly confirmed by the examiner during the original prosecution of a related patent.
  • Expectation of Success: Petitioner argued that success was predictable because both Thia's system and Satran's iSCSI protocol were described in the context of the Open Systems Interconnection (OSI) network model. Furthermore, Thia was explicitly designed to be adapted for existing communication protocols with only minor software modifications, providing an easy migration path for protocols like iSCSI.

Ground 2: Obviousness over Thia, Satran, and Carmichael - Claims 24-26 are obvious over Thia in view of Satran and Carmichael.

• Prior Art Relied Upon: Thia, Satran, and Carmichael (Patent 5,894,560).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground builds on the Thia/Satran combination by adding the teachings of Carmichael to address limitations in dependent claims 24-26. Petitioner argued Carmichael disclosed the key limitation of claim 24, which requires that an iSCSI read request be "accompanied by an indication of where the destination memory is located on the host computer." Carmichael teaches using Direct Memory Access (DMA) with physical region descriptor (PRD) tables and scatter-gather lists to efficiently manage data transfers. The petition asserted that a scatter-gather list serves as the claimed "indication." The petition also argued that Carmichael teaches passing this indication from the host to the interface device before the data response is received, meeting the additional limitation of claim 26.
  • Motivation to Combine: A POSITA would combine Carmichael's teachings with the Thia/Satran system to improve the efficiency of its DMA operations. The petition contended that because the Thia/Satran system and Carmichael's invention are both directed at improving data processing speed and efficiency, combining their respective hardware offloading and memory management techniques was a logical and obvious step to achieve a more optimized system at minimal cost.
  • Expectation of Success: Petitioner argued this combination was predictable. Carmichael's DMA methods were designed to be compatible with various operating systems and storage protocols, and a POSITA would have reasonably expected to integrate them into an iSCSI-based system like the one formed by Thia and Satran to gain efficiency benefits.

4. Arguments Regarding Discretionary Denial

• The petition was filed concurrently with a motion for joinder to two previously instituted IPRs (IPR2017-01405 and IPR2017-01735) that challenged the same patent on identical grounds. Petitioner argued that joinder is explicitly permitted by statute, would promote administrative efficiency, and would avoid the risk of inconsistent results, making discretionary denial under §314(a) inappropriate.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 3, 9-10, 16, 22, 24-30, and 35-36 of the ’205 patent as unpatentable under 35 U.S.C. §103.