PTAB

IPR2018-00372

Dell Inc. v. Alacritech, Inc.

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1. Case Identification

  • Case #: IPR2018-00372
  • Patent #: 7,337,241
  • Filed: December 27, 2017
  • Petitioner(s): Intel Corporation
  • Patent Owner(s): Alacritech, Inc.
  • Challenged Claims: 1-24

2. Patent Overview

  • Title: Fast-Path Apparatus for Receiving Data Corresponding to a TCP Connection
  • Brief Description: The ’241 patent relates to offloading Transmission Control Protocol (TCP) processing from a host computer to an intelligent network interface card (INIC). The patent described an INIC with a "fast-path" to process packets for established connections directly on the card, bypassing the host's protocol stack, and a "slow-path" where packets are handled conventionally by the host.

3. Grounds for Unpatentability

Ground 1: Obviousness over Erickson, Tanenbaum96, and Alteon - Claims 1-8, 18, 22, and 23 are obvious over Erickson in combination with Tanenbaum96 and Alteon.

  • Prior Art Relied Upon: Erickson (Patent 5,768,618), Tanenbaum96 (a 1996 computer networking textbook), and Alteon (a 1997 technical brief on Gigabit Ethernet adapters).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Erickson taught a foundational I/O device adapter that performs fast-path network protocol processing using header templates, but focused its examples on the User Datagram Protocol (UDP). Tanenbaum96, a widely-cited textbook, supplied the well-known details for adapting Erickson's system to TCP, including fast-path processing using prototype headers and connection records. The combination allegedly taught sorting packets into fast and slow paths. To meet the "without an interrupt dividing" limitation of independent claim 1, Petitioner cited Alteon, which disclosed an intelligent adapter that processes multiple data packets and issues only a single interrupt to the host, thereby teaching that header validation for multiple layers could occur without an intervening host interrupt. For the limitation of sending data directly to application memory without headers, Petitioner pointed to Erickson's direct application interface and Alteon's disclosure of moving data "minus the header" to application memory.
    • Motivation to Combine: A person of ordinary skill in the art (POSITA) would combine Erickson with Tanenbaum96 because Erickson expressly incorporated an earlier edition of the Tanenbaum textbook by reference, directing a POSITA to it for details on TCP. Given the prevalence of TCP, a POSITA would have been motivated to consult the current (1996) edition to implement a TCP-capable fast-path adapter. A POSITA would combine Alteon to solve the shared goal of reducing host processor intervention, as Alteon’s single-interrupt method was a known technique for improving performance in the precise manner sought by Erickson.
    • Expectation of Success: A POSITA would have a high expectation of success because the combination involved applying well-known TCP principles (from Tanenbaum96) and a known performance-enhancing technique (from Alteon) to an existing adapter architecture (Erickson) to achieve the predictable result of an efficient, TCP-capable, low-interrupt network adapter.

Ground 2: Obviousness over Erickson and Tanenbaum96 - Claims 9-17, 19-21, and 24 are obvious over Erickson in combination with Tanenbaum96.

  • Prior Art Relied Upon: Erickson (Patent 5,768,618) and Tanenbaum96 (a 1996 computer networking textbook).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground focused on transmit-side claims (e.g., independent claims 9 and 17). Petitioner argued that Erickson taught the core method of network communication by obtaining data from a host processor, prepending a header from a template using a second processor (the I/O adapter), and transmitting the resulting packets. While Erickson detailed this for UDP, Tanenbaum96 provided the necessary, well-understood TCP-specific teachings. These included dividing data into multiple segments, establishing a TCP connection via a handshake, and using a prototype header for fast-path transmission, mapping directly to the limitations of the transmit claims.
    • Motivation to Combine: The motivation was identical to Ground 1. Erickson's express reference to Tanenbaum and the commercial importance of TCP would motivate a POSITA to implement Erickson's fast-path transmission system for TCP, using the standard techniques described in Tanenbaum96.
    • Expectation of Success: A POSITA would have a high expectation of success in implementing a TCP transmit path, as it merely involved substituting the well-documented, standardized steps of TCP segmentation and connection management for the UDP steps in Erickson's exemplary embodiment.

  • Additional Grounds: Petitioner asserted a third ground that claims 18, 22, and 23 are obvious over Erickson in combination with Tanenbaum96 and Alteon, which relied on the same prior art and rationale as Ground 1 but was directed to a different subset of claims.

4. Key Claim Construction Positions

  • "[first/second] mechanism": Petitioner argued that this term, appearing in claims such as 1, 3, 9, and 17, is a nonce word that fails to recite a sufficiently definite structure for performing the claimed functions (e.g., "processing the packets," "dividing the data"). Therefore, Petitioner contended the term should be construed under 35 U.S.C. §112(6) as a means-plus-function limitation. Because the specification allegedly fails to disclose the necessary corresponding structure or algorithm to perform these functions, Petitioner argued that claims containing this term are indefinite.
  • "without an interrupt dividing": Petitioner argued that this phrase, found in limitations of claims 1, 18, and 22, is indefinite. The argument was that the patent's "fast-path" processing occurs on the INIC, separate from the host processor. A host processor interrupt, therefore, could not "divide" processing that is not occurring on the host. Petitioner contended that a POSITA would not understand what it means for an interrupt on one processor to divide the processing on another, rendering the limitation nonsensical and the claims indefinite.

5. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1-24 of Patent 7,337,241 as unpatentable.