Cavium Inc v. Alacritech Inc

1. Case Identification

• Case #: IPR2018-00403
• Patent #: 8,805,948
• Filed: December 27, 2017
• Petitioner(s): Cavium, Inc.
• Patent Owner(s): Alacritech, Inc.
• Challenged Claims: 1, 3, 6-8, 17, 19, 21-22

2. Patent Overview

• Title: Intelligent Network Interface System and Method for Protocol Processing
• Brief Description: The ’948 patent discloses a system for offloading Transmission Control Protocol (TCP) processing from a host computer to an intelligent network interface card (INIC). The INIC employs a "fast path" to bypass the host's protocol stack for normal data packets and a "slow path" to direct packets with exception conditions to the host for conventional processing.

3. Grounds for Unpatentability

Ground 1: Claims 1, 3, 6-8, 17, 19, and 21-22 are obvious over Thia in view of Tanenbaum96 and Stevens2.

• Prior Art Relied Upon: Thia (a 1995 article on a Reduced Operation Protocol Engine), Tanenbaum96 (a 1996 textbook, Computer Networks, 3rd ed.), and Stevens2 (a 1995 textbook, TCP/IP Illustrated, Vol. 2).
• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner argued that the combination of these references taught every limitation of the challenged claims. Thia was asserted to provide the foundational architecture: a network interface with a hardware-based "fast path" (a Reduced Operation Protocol Engine, or "ROPE" chip) that bypasses a host's standard protocol stack ("slow path") for normal packets. Thia's system performs a "receive bypass test" to differentiate normal packets from exception packets and uses direct memory access (DMA) to move processed payload data directly to host memory.

    Petitioner contended that a person of ordinary skill in the art (POSITA) would have looked to standard TCP/IP textbooks like Tanenbaum96 and Stevens2 to implement Thia's general offload concept for the then-dominant TCP/IP protocol. These references allegedly provided the specific conditions for Thia's "bypass test" through their detailed explanation of the well-known "Header Prediction" algorithm. Tanenbaum96 and Stevens2 taught that Header Prediction involves checking for specific "exception conditions" to identify normal packets eligible for fast-path processing. These conditions included verifying the TCP connection is in the ESTABLISHED state and confirming the absence of special flags (e.g., FIN, SYN, RST), IP fragmentation, and out-of-order sequence numbers.

    The combination, Petitioner argued, taught the claimed method and apparatus. The network interface (Thia's ROPE/NIA) would check for the exception conditions (Tanenbaum96/Stevens2). If no exceptions were found, the interface would bypass the host stack, remove the TCP header, and store the payload data in order within a host buffer via DMA (Thia). If an exception was found, the packet would be directed to the host's protocol processing stack for handling (Thia's slow path). This mapping was applied to independent method claim 1 and apparatus claim 17, with the logic extending to the dependent claims which add features explicitly taught by the combination, such as using DMA (claim 3, 19) and checking for specific RST and SYN flags (claims 7, 8, 21, 22).

  • Motivation to Combine: A POSITA would combine these references to solve the well-known problem of host CPU overhead caused by network protocol processing. Petitioner argued that it would have been obvious to apply Thia's efficient hardware offload architecture to the most prevalent protocol, TCP/IP. Because Thia's bypass test is described as a generalization of Jacobson's Header Prediction algorithm, a POSITA would have been directly motivated to consult definitive guides on that algorithm, like Tanenbaum96 and Stevens2, to implement the specific checks required for TCP/IP packets. The combination was presented as a predictable fusion of known solutions to a known problem.

  • Expectation of Success: Petitioner asserted that a POSITA would have had a high expectation of success. The combination involved applying well-understood, widely implemented technologies—hardware protocol offload, the standard TCP/IP protocol, the Header Prediction algorithm, and DMA—which were all mature concepts at the time of the invention.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under 35 U.S.C. §314(a) or §325(d) would be inappropriate. This petition was a refiling of a prior petition (IPR2017-01729) which the Board had denied at institution. Petitioner asserted the denial was on the sole, non-merits basis that the prior petition failed to adequately prove the public accessibility of the Stevens2 reference. Because the Board never substantively reviewed the asserted prior art or invalidity arguments, Petitioner contended that this new petition, which included new evidentiary declarations to cure the prior deficiency, was not redundant and would not be an inefficient use of Board resources.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1, 3, 6-8, 17, 19, and 21-22 of Patent 8,805,948 as unpatentable.