PTAB

IPR2018-00436

STMicroelectronics Inc v. Lone Star Silicon Innovations LLC

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Method of Forming a Contact Hole in an Interlevel Dielectric Layer Using Dual Etch Stops
  • Brief Description: The ’188 patent discloses a method for fabricating semiconductor devices, specifically for forming contact holes through an interlevel dielectric layer to an underlying source/drain region. The method uses a three-layer dielectric structure and three sequential, highly selective etches, employing two of the layers as distinct etch stops to prevent damage to the underlying silicon substrate.

3. Grounds for Unpatentability

Ground 1: Obviousness over Kawai - Claims 1-5, 7-13, 15-19, 21-23, and 25-27 are obvious over Kawai in view of the knowledge of a person of ordinary skill in the art (POSA).

  • Prior Art Relied Upon: Kawai (Japanese Patent Publication No. JPH8-46173).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Kawai discloses all limitations of the challenged claims. Kawai is directed to the same problem of forming small, stable contact holes in DRAM manufacturing. It explicitly teaches a method comprising a three-layer interlevel dielectric (silicon oxide, silicon nitride, silicon oxide) and a corresponding three-step sequential etch process to form a contact hole. Petitioner asserted that Kawai’s first etch uses the second (nitride) layer as an etch stop, and the second etch uses the third (oxide) layer as an etch stop, mirroring the dual etch stop process of the ’188 patent. The detailed mapping covered the formation of the substrate, gate, and source/drain regions, the deposition of the three dielectric layers, the use of a photoresist etch mask, and the sequential application of highly selective etches to create the contact hole down to the source/drain region.
    • Motivation to Combine (for §103 grounds): This ground primarily relied on a single reference. Petitioner argued that any minor distinctions would have been obvious to a POSA. For instance, to the extent Kawai did not explicitly state the third etch was "highly selective" relative to the underlying substrate, Petitioner contended a POSA would have been motivated to use a known selective etch chemistry (like the C4F8/O2 process disclosed in Kawai) to achieve the reference's stated goal of protecting the underlying layer and preventing damage, a key objective in semiconductor manufacturing.
    • Expectation of Success (for §103 grounds): A POSA would have had a high expectation of success in applying the well-understood, highly selective etching processes described in Kawai to reliably form contact holes without damaging the substrate, as this was the explicit purpose of such multi-step etch processes.

Ground 2: Obviousness over Kawai in view of Sung - Claims 20, 28, and 29 are obvious over Kawai in view of Sung.

  • Prior Art Relied Upon: Kawai (Japanese Patent Publication No. JPH8-46173) and Sung (Patent 5,550,078).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground addressed dependent claims related to subsequent processing steps not fully detailed in Kawai. Claim 28 requires planarizing the dielectric layer using chemical-mechanical polishing (CMP). Claim 20 and 29 add forming a conductive plug and a "metal-1 pattern" on the first dielectric layer to contact the plug. Petitioner argued that while Kawai teaches the core DRAM structure, Sung explicitly teaches these conventional finishing steps. Sung discloses using CMP to create a smooth, planar surface on an interlevel dielectric before subsequent processing, and then forming a conductive plug in the contact hole and creating a metal-1 layer to provide interconnection.
    • Motivation to Combine (for §103 grounds): A POSA would combine these references because both relate to DRAM fabrication and address complementary aspects of the overall process. A POSA implementing Kawai's method for forming contact holes would have been motivated to look to conventional and well-known techniques, such as those taught by Sung, to complete the DRAM device. This includes using CMP to improve process reliability and forming the necessary metal interconnects (metal-1 layer) to make the device functional.
    • Expectation of Success (for §103 grounds): Petitioner asserted a high expectation of success, as combining Sung's standard planarization and metallization steps with Kawai's contact formation method was a routine integration of known, predictable semiconductor manufacturing processes.

4. Key Claim Construction Positions

  • Source/Drain Contact: Petitioner proposed this term be construed as "a contact area used to electrically couple a conductive member (for example, a conductive plug) to the source/drain region." Petitioner argued that the specification and claims of the ’188 patent support that this "contact" is not necessarily a separate structure but can be the top surface of the source/drain region itself. This construction was important to show that prior art references disclosing a conductive plug landing directly on a source/drain region met this claim limitation.

5. Arguments Regarding Discretionary Denial

  • The petition was filed concurrently with a motion for joinder to an already-instituted IPR proceeding (IPR2017-01561) involving the same patent and substantially identical grounds. Petitioner’s request for joinder served as a primary argument for why discretionary denial would be inappropriate, promoting administrative efficiency by consolidating related challenges.

6. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1-5, 7-13, 15-19, 21-23, and 25-29 of the ’188 patent as unpatentable.