VIZIO, Inc. v. ATI Technologies ULC

1. Case Identification

• Patent #: 7,633,506
• Filed: February 1, 2018
• Petitioner(s): VIZIO, Inc.
• Patent Owner(s): ATI Technologies ULC
• Challenged Claims: 1-9

2. Patent Overview

• Title: PARALLEL PIPELINE GRAPHICS SYSTEM
• Brief Description: The ’506 patent describes a graphics processing chip architecture that utilizes multiple parallel processing pipelines to render images. The allegedly novel aspect is that each parallel pipeline comprises a "unified shader" that is programmable to perform both color shading and texture shading operations within a single, integrated circuit.

3. Grounds for Unpatentability

Ground 1: Obviousness over Papakipos and Gibson - Claims 1-2 and 6-9 are obvious over Papakipos in view of Gibson.

• Prior Art Relied Upon: Papakipos (Patent 6,532,013) and Gibson (Patent 6,750,867).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Papakipos taught all elements of independent claim 1 except for the use of multiple parallel pipelines and tiling. Specifically, Papakipos disclosed a complete graphics chip architecture with a front-end and a back-end, and its “Shader Module 406” was argued to be the claimed "unified shader" because it performs interwoven color shading (e.g., calculating diffuse/specular colors) and texture shading (e.g., texture mapping) in a programmable, iterative manner. Gibson was cited to supply the missing parallel processing elements, as it explicitly taught using dual rendering devices (pipelines) in parallel and dividing the screen into tiles to distribute the processing load and improve performance. Dependent claim 2 (FIFO unit for load balancing) and claims 6-9 (setup unit, scan converter, rasterizer, texture unit, looping functionality) were argued to be disclosed or rendered obvious by features inherent to Papakipos's architecture or as logical additions when implementing Gibson's parallel system.
  • Motivation to Combine: A person of ordinary skill in the art (POSITA) would combine the advanced, unified shader architecture of Papakipos with the parallel processing and tiling system of Gibson for the predictable purpose of increasing graphics processing performance. Gibson expressly taught that using dual rendering devices improves system performance, providing a clear motivation to apply this well-known technique to other graphics pipelines like the one in Papakipos.
  • Expectation of Success: A POSITA would have a reasonable expectation of success because both references operate in the same field of graphics pipelines, and implementing parallel processors was a routine and well-understood method for optimizing performance. Duplicating Papakipos’s shader module and using Gibson's tiling for load balancing would have been a matter of routine engineering.

Ground 2: Obviousness over Papakipos, Gibson, and Zhu - Claims 3-5 are obvious over Papakipos and Gibson, in further view of Zhu.

• Prior Art Relied Upon: Papakipos (Patent 6,532,013), Gibson (Patent 6,750,867), and Zhu (Patent 6,697,063).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground built upon the combination of Papakipos and Gibson to address dependent claims 3-5, which added limitations for Z-buffering. Petitioner argued that while Papakipos and Gibson provided the base parallel unified shader system, Zhu taught the specific Z-buffering features. Zhu was cited for its disclosure of a "z buffer logic unit" and a "color buffer logic unit" (claim 3). For claim 4, Zhu taught interfacing the z buffer logic unit with the scan converter via both a "hierarchical Z interface" and an "early Z interface" to remove non-visible fragments early in the pipeline. For claim 5, Zhu taught interfacing the z buffer logic unit with the shader through a "late Z interface" (a final depth buffer) to correctly handle transparent geometries after shading.
  • Motivation to Combine: A POSITA building the parallel system of Papakipos and Gibson would be motivated to incorporate Zhu’s advanced “double-z” buffering scheme to improve efficiency. Zhu itself explained that its approach had advantages over existing methods (like the one incorporated by reference in Papakipos) by reducing raster/shading requirements, providing a direct reason for its inclusion.
  • Expectation of Success: Combining these known buffering techniques from Zhu into the established parallel pipeline of Papakipos/Gibson would have been a predictable implementation, as Z-buffering was a standard function in graphics processing.

Ground 3: Obviousness over Papakipos, Gibson, and Donham - Claims 1-2 and 6-9 are obvious over Papakipos and Gibson, in further view of Donham.

• Prior Art Relied Upon: Papakipos (Patent 6,532,013), Gibson (Patent 6,750,867), and Donham (Patent 6,980,209).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground was presented as an alternative to Ground 1, primarily to fortify the argument for the "unified shader" limitation. Petitioner asserted that Donham provided an even more explicit disclosure of a unified shader. Donham's "Pixel Shader 30" was argued to have a nearly identical architecture to the unified shader depicted in the ’506 patent itself. It received rasterized data, performed both color shading (blending values) and texture shading (texture/bump mapping) using internal "Microblenders" (math units), and sent the final pixels to a frame buffer.
  • Motivation to Combine: This combination was motivated by the desire to implement a known shader circuit with detailed functionality into the parallel architecture of Papakipos and Gibson. A POSITA would look to established shader designs like Donham for a robust and proven way to implement the functionality of the shader module discussed in Papakipos. This was presented as an alternative to rebut potential arguments that Papakipos’s disclosure of a unified shader was insufficient.
• Additional Grounds: Petitioner asserted an additional obviousness challenge (Ground 4) for claims 3-5 based on the combination of Papakipos, Gibson, Donham, and Zhu. This ground leveraged Donham for a more explicit teaching of the "unified shader" while using Zhu to teach the specific Z-buffering limitations, relying on the same motivations to combine presented in Grounds 2 and 3.

4. Key Claim Construction Positions

• Petitioner's arguments centered on the term "unified shader." The petition was filed in the context of a co-pending ITC investigation where the Patent Owner had argued for a narrow construction of this term, suggesting Papakipos was insufficient prior art.
• Petitioner argued that under the Broadest Reasonable Interpretation (BRI) standard applicable in an IPR, the plain and ordinary meaning should apply.
• To preemptively address the potential for a narrow construction, Petitioner presented Ground 3 (adding Donham), arguing that Donham's "Pixel Shader 30" indisputably met even a narrower definition of a "single shader circuit" that performs both color and texture shading, as its disclosed architecture was nearly identical to that shown in the ’506 patent.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-9 of the ’506 patent as unpatentable.