PTAB

IPR2018-00799

Samsung Electronics Co Ltd v. Tessera Advanced Technologies Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Semiconductor Device Including A Diffusion Layer Formed Between Electrode Portions
  • Brief Description: The ’001 patent discloses a semiconductor device, such as a Chip Size Package (CSP), designed to improve connection reliability. The technology addresses the formation of a brittle tin-copper (Sn-Cu) intermetallic diffusion layer that occurs when a tin-based solder ball is attached to a copper electrode, proposing a structure that manages this layer to prevent connection failures caused by thermal stress.

3. Grounds for Unpatentability

Ground 1: Obviousness over Kimura and Takizawa - Claims 1-4, 6-8, 10-13, and 15-17 are obvious over Kimura in view of Takizawa.

  • Prior Art Relied Upon: Kimura (Japanese Unexamined Patent Application Bulletin No. JP-2001-118957-A) and Takizawa (Japanese Patent Application Publication No. 2000-260894).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Kimura disclosed the core structure of the challenged claims: a semiconductor device with a copper "first electrode portion" (lands and wires) and a tin-based solder ball "second electrode portion." Petitioner asserted that the reflow process described in Kimura would necessarily form the claimed "diffusion layer" between the copper and tin components. To the extent Kimura's disclosure of the diffusion layer was insufficient, Takizawa was introduced as it explicitly taught forming a strong Cu-Sn alloy diffusion layer to improve reliability and prevent cracking. For claim 10, which requires a combined thickness of the first electrode and diffusion layer of 10-20 µm, Petitioner contended that combining the thickness of Kimura's first electrode (10.7-15.7 µm) with the optimized diffusion layer thickness taught by Takizawa (1.87-4.0 µm) results in a total thickness that falls squarely within the claimed range.
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSA) would combine Kimura's device with Takizawa's teachings to solve the well-known problem of solder joint reliability. Both references operated in the same technical field, addressed solder ball detachment, and used similar manufacturing processes. Takizawa’s specific teachings on optimizing the diffusion layer thickness provided a direct solution to improve the reliability of a device like that disclosed in Kimura.
    • Expectation of Success: Petitioner asserted that a POSA would have had a high expectation of success. The combination involved applying a known technique (optimizing a diffusion layer) to a conventional semiconductor structure to achieve the predictable result of enhanced connection strength.

Ground 2: Obviousness over Kimura, Takizawa, and Nozawa - Claims 9 and 18 are obvious over Kimura in view of Takizawa and further in view of Nozawa.

  • Prior Art Relied Upon: Kimura (Japanese Unexamined Patent Application Bulletin No. JP-2001-118957-A), Takizawa (Japanese Patent Application Publication No. 2000-260894), and Nozawa (Patent 6,181,010).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon the combination in Ground 1 to address the limitations of claims 9 and 18, which further require connecting the device to "a substrate having a wiring electrode." Petitioner argued that a POSA would inherently understand that Kimura’s device was intended to be mounted on such a substrate to be useful. To make this explicit, Petitioner introduced Nozawa, which clearly disclosed connecting a similar semiconductor device via its solder bumps to a circuit board substrate having a copper interconnect pattern. This combination, Petitioner argued, supplied the final limitation of claims 9 and 18.
    • Motivation to Combine: The motivation to add the teachings of Nozawa was to render the device of Kimura and Takizawa functional for its intended purpose. A POSA would have known that a chip-scale package is not a standalone product and must be connected to an external substrate, such as a printed circuit board (PCB), to function. Nozawa simply provided an explicit teaching of this conventional and necessary step.
    • Expectation of Success: Connecting a semiconductor package to a substrate was a routine, well-understood, and predictable process for a POSA. Therefore, applying Nozawa’s teachings to the Kimura/Takizawa device would be expected to yield a successful and functional assembly.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial would be improper because this petition was not cumulative to other proceedings. It was asserted that the grounds were materially different from those in a prior inter partes review (IPR) filed by Broadcom (IPR2017-01486), which had since been terminated. Furthermore, Petitioner stated that because Samsung was not a party to the Broadcom IPR, this petition did not represent an improper "follow-on" attempt, and the factors from NVIDIA Corp. v. Samsung Elec. Co. weighed in favor of institution.

5. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1-4, 6-13, and 15-18 of the ’001 patent as unpatentable under 35 U.S.C. §103.